This guide will show you how to repurpose your tile for a Verilog-based project instead of a Wokwi one. This is suitable if you know some Verilog and want to submit a Verilog design, but already have submitted a Wokwi project to the shuttle.


Add your design source files, documentation and update info.yaml. Commit these files to the newly created repo.
Iterate on your design until the GDS and Docs actions go green.
Go to app.tinytapeout.com, click on your project name, then click on the big blue “SUBMIT A REVISION” button.