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Silicon proven projects
Digital Design Guide
Getting started with our digital design tool
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Logic Gates
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Customisable Design - Padlock
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Customisable Design - 7-Seg
Simple automated testing using truth tables
Generating Wokwi designs from truth tables
How do semiconductors work?
Introduction to SiliWiz
Draw a Resistor
Parasitics
Voltage Divider
Draw a capacitor
Draw an N MOSFET
Making a logic inverter
Draw a P type MOSFET
Draw a CMOS inverter
Making ASICs
Working with HDLs
Important!
FPGA to ASIC
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Local hardening
Testing Projects with the Analog Discovery
Updating your project documentation
Workshop
1 - Draw your own MOSFET
2 - Simulate a logic gate
3 - Create the GDS
4 - Submit your design
5 - Optional - Activate and Test a Design
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Tiny Tapeout
>
Working with HDLs
> HDL templates
HDL templates
Verilog
https://github.com/TinyTapeout/ttihp-verilog-template
This repo shows how to:
specify the files
for building the ASIC
run an automatic test
when you push new code to the repo