Tiny Tapeout > Working with HDLs > HDL templates

HDL templates

Verilog

For the IHP shuttle use: https://github.com/TinyTapeout/ttihp-verilog-template
For the SKY shuttle use: https://github.com/TinyTapeout/ttsky-verilog-template

This repo shows how to:

specify the files for building the ASIC
run an automatic test when you push new code to the repo

User contributed templates

Chisel

https://github.com/TinyTapeout/ttihp-chisel-template