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Digital Design Guide
Getting started with our digital design tool
Holidays
Logic Gates
Logic Puzzle - Flip Flop
Logic Puzzle - Edge Detect
Logic Puzzle - Full Adder
Logic Puzzle - Padlock
Customisable Design - Padlock
Customisable Design - UART
Customisable Design - 7-Seg
Simple automated testing using truth tables
Generating Wokwi designs from truth tables
How do semiconductors work?
Introduction to SiliWiz
Draw a Resistor
Parasitics
Voltage Divider
Draw a capacitor
Draw an N MOSFET
Making a logic inverter
Draw a P type MOSFET
Draw a CMOS inverter
Making ASICs
Working with HDLs
Important!
FPGA to ASIC
HDL resources
HDL templates
Testing your design
Competitions
Demoscene
Guides
TT04+ demoboard quickstart
Local hardening
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Clock
GPIO pins
Analog pins
Memory
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PCB (TT04+)
PCB (TT02-03)
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> 128 YaFPGA
128 YaFPGA
128 : YaFPGA
Select Project
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ON
SW2
Author: Frans Skarman
Description: Yet another FPGA
GitHub repository
Clock: 1000 Hz
How it works
TODO
How to test
TODO
IO
#
Input
Output
0
clock
output0
1
input1
output1
2
input2
output2
3
input3
output3
4
input4
5
config data
6
config clock
7