79 Sparsity Aware Matrix Vector Multiplication

79 : Sparsity Aware Matrix Vector Multiplication

  • Author: Test
  • Description: Count up to 10, one second at a time.
  • GitHub repository
  • Clock: 10000000 Hz

How it works

Uses a set of registers to divide the clock, and then some combinational logic to convert from binary to decimal for the display.

Puts the bottom 8 bits of the counter on the bidirectional outputs.

With all the inputs set to 0, the internal 24 bit compare is set to 10,000,000. This means the counter will increment by one each second.

If any inputs are non zero, then the input will be used as an bits 11 to 18 of the 24 bit compare register. Example: setting the inputs to 00010000 will program 16384 into the compare register. With a 10MHz clock the counter will increment ~610 times per second.

How to test

After reset, the counter should increase by one every second with a 10MHz input clock. Experiment by changing the inputs to change the counting speed.

IO

#InputOutputBidirectional
0compare bit 11segment asecond counter bit 0
1compare bit 12segment bsecond counter bit 1
2compare bit 13segment csecond counter bit 2
3compare bit 14segment dsecond counter bit 3
4compare bit 15segment esecond counter bit 4
5compare bit 16segment fsecond counter bit 5
6compare bit 17segment gsecond counter bit 6
7compare bit 18dotsecond counter bit 7

Chip location

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