107 REBEL-2 Balanced Ternary ALU

107 : REBEL-2 Balanced Ternary ALU

  • Author: Ole Christian Moholth and Steven Bos
  • Description: This 2-trit balanced ternary ALU is part of the REBEL-2 balanced ternary logic CPU
  • GitHub repository
  • Clock: 0 Hz

How it works

WIP. This balanced ternary ALU has several operations based on a novel REBEL-2 ISA. Operations include MIN,MAX,ADD,SUB,MUL,CMP,SHFT and can be done trit-wise or word-wise. This project is designed, generated and verified with Mixed Radix Circuit Synthesizer (MRCS).

How to test

There are many automated test included for MRCS. A verilog testbench for FPGA and FPGA constraint file is WIP.

Picture

IO

#InputOutputBidirectional
0ui_in[7] func2Huo_out[7] carryHuio_in[7] b0H
1ui_in[6] func2Luo_out[6] carryLuio_in[6] b0L
2ui_in[5] func1Huo_out[5] out1Huio_in[5] a1H
3ui_in[4] func1Luo_out[4] out1Luio_in[4] a1L
4ui_in[3] func0Huo_out[3] out0Huio_in[3] a0H
5ui_in[2] func0Luo_out[2] out0Luio_in[2] a0L
6ui_in[1] b1Huo_out[1] unuseduio_in[1] unused
7ui_in[0] b1Luo_out[0] unuseduio_in[0] unused

Chip location

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