715 SPI Peripheral

715 : SPI Peripheral

  • Author: Mike Bell
  • Description: SPI RAM/ROM/Random source
  • GitHub repository
  • Clock: 10000000 Hz

How it works

The project implements an 8 byte RAM, 324 byte ROM and a random source supporting standard SPI read/write (03h/02h) and SPI quad read/write (6Bh/32h) commands. The quad read commands have 2 delay cycles.

The address map is:

Address Item
0x000 RP2040 boot stage 2 ROM
0x100 8 byte RAM, wrapped 32 times
0x200 RP2040 program ROM
0x300 Mirror of the RAM
0x400 Random source

See the README for more details.

Note the default project clk is a debug clock only, the project is internally clocked off SPI CLK, input 0.

How to test

You will need to use an SPI/QSPI master, unfortunately it was not possible to set up the pinout to support both QSPI and match the native RP2040 SPI block, so you'll need a PIO (Q)SPI implementation. I'll make that available before the chips are available.

The values in the RAM may be inspected by setting the address on the input toggle switches 2-5 and pressing the single clock button to latch the data, which is displayed on the 7 segment display and presented on uio pins 4-7. The default project clock should otherwise not be used - the project is clocked from the SPI clock.

The project is also designed to be used as a ROM connected to an RP2040's QSPI pins (instead of the more normal flash). You'll need a custom board for this as the QSPI pins are generally connected directly to a flash chip, I have a couple which I could potentially send to interested people in the UK - contact me on Discord.

External hardware

A custom RP2040 board to make full use of the ROM

IO

#InputOutputBidirectional
0SPI CLKsegment aSPI MOSI / D0
1SPI CSnsegment bSPI MISO / D1
2Debug nibble selectsegment cD2
3Debug addr 0segment dD3
4Debug addr 1segment eDebug bit 0
5Debug addr 2segment fDebug bit 1
6segment gDebug bit 2
7dot (Set to SPI CSn)Debug bit 3

Chip location

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