421 RISC-V Mini IHP
421 : RISC-V Mini IHP
- Author: Thomas Uehlinger
- Description: RISC-V Mini 8 Bit on IHP
- GitHub repository
- Open in 3D viewer
- Clock: 100000 Hz
How it works
This project implements RISC-V Mini by RickGao (https://github.com/RickGao/RISC-V-Mini), a compact 8-bit RISC-V processor core optimized for Tiny Tapeout, a fabrication platform for small-scale educational IC projects. The processor employs a customized, compressed RISC-V instruction set (RVC) to reduce instruction width to 16 bits, leading to a more compact design suited to Tiny Tapeout's area and resource constraints. Developed in Verilog, this processor will handle computational, load/store and control-flow operations efficiently and undergo verification through simulation and testing.
### Processor Components
The processor comprises the following core components, optimized to meet Tiny Tapeout’s area requirements:
- Control Unit Generates control signals for instruction execution based on opcode and other instruction fields.
- Register File Contains 8 general-purpose, 8-bit-wide registers. Register x0 will always return zero when read, adhering to RISC-V convention.
- Arithmetic Logic Unit (ALU) Performs basic arithmetic (addition, subtraction) and logical (AND, OR, XOR, SLT) operations as specified by the decode stage. Supports custom compressed RISC-V instructions.
- Datapath Single-cycle execution, optimized for minimal hardware complexity, reducing the processor’s area and power consumption.
How to test
Simply set the input to the instruction and clock once to receive the output.
-
R-Type, I-Type, and L-Type instructions will output 0.
-
The S-Type instruction will output the value of the register.
-
The B-Type instruction will output 1 if the branch is taken and 0 if it is not taken.
Instructions List
R-Type
| Name | funct3 [15:13] | funct2 [12:11] | rs2 [10:8] | rs1 [7:5] | rd [4:2] | Opcode(00) |
|---|---|---|---|---|---|---|
| AND | 000 | 00 | XXX | XXX | XXX | Opcode(00) |
| OR | 001 | 00 | XXX | XXX | XXX | Opcode(00) |
| ADD | 010 | 00 | XXX | XXX | XXX | Opcode(00) |
| SUB | 011 | 00 | XXX | XXX | XXX | Opcode(00) |
| XOR | 001 | 01 | XXX | XXX | XXX | Opcode(00) |
| SLT | 111 | 00 | XXX | XXX | XXX | Opcode(00) |
#### I-Type
| Name | funct3 [15:13] | Imm [12:8] (5-bit unsigned) | rs1 [7:5] | rd [4:2] | Opcode(01) |
|---|---|---|---|---|---|
| SLL | 100 | XXXXX | XXX | XXX | Opcode(01) |
| SRL | 101 | XXXXX | XXX | XXX | Opcode(01) |
| SRA | 110 | XXXXX | XXX | XXX | Opcode(01) |
| ADDI | 010 | XXXXX | XXX | XXX | Opcode(01) |
| SUBI | 011 | XXXXX | XXX | XXX | Opcode(01) |
L-Type
| Load | Imm [15:8] (8-bit signed) | 000 | rd [4:2] | Opcode(10) |
|---|
S-Type
| Store | 00000 | 000 | rs1 [7:5] | 000 | Opcode(11) |
|---|
B-Type
| Name | funct3 [15:13] | funct2 [12:11] | rs2 [10:8] | rs1 [7:5] | 000 | Opcode(11) |
|---|---|---|---|---|---|---|
| BEQ | 011 | 00 | XXX | XXX | 000 | Opcode(11) |
| BNE | 011 | 10 | XXX | XXX | 000 | Opcode(11) |
| BLT | 111 | 00 | XXX | XXX | 000 | Opcode(11) |
External hardware
No external hardware.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | instruction[0] | result[0] | instruction[8] |
| 1 | instruction[1] | result[1] | instruction[9] |
| 2 | instruction[2] | result[2] | instruction[10] |
| 3 | instruction[3] | result[3] | instruction[11] |
| 4 | instruction[4] | result[4] | instruction[12] |
| 5 | instruction[5] | result[5] | instruction[13] |
| 6 | instruction[6] | result[6] | instruction[14] |
| 7 | instruction[7] | result[7] | instruction[15] |