This is a 8 bit pseudo-random number generator. First, the chip clock is divided down by 14 cascaded divide-by-two stages. This chain results in a total division factor of 16'384. For a chip clock of 10 kHz, a frequency of 0.61 Hz results. This local slow clock drives four Fibonacci maximum-length linear shift registers (LFSRs) with 9, 10, 11, and 13 bits. To minimize correlations, these LFSRs are selected such that the sequence lengths are relative prime. For the final output, these four LFSR sequences are combined with XOR operations to generate 8 bits.
The pseudo-random output bits can be observed with a 7-segment LED display, an oscilloscope, or a logic analyzer.
A 7-segment LED display is recommended
# | Input | Output | Bidirectional |
---|---|---|---|
0 | Random bit output 0 | ||
1 | Random bit output 1 | ||
2 | Random bit output 2 | ||
3 | Random bit output 3 | ||
4 | Random bit output 4 | ||
5 | Random bit output 5 | ||
6 | Random bit output 6 | ||
7 | Random bit output 7 |