519 3-bit up-down counter
519 : 3-bit up-down counter
- Author: Nefeli Metallidou
- Description: A 3-bit up-down counter
- GitHub repository
- Open in 3D viewer
- Clock: 50000000 Hz
How it works
A 3-bit up/down counter with a reset signal, enable signal, load signal, and up/down signal.
When the rst is low, the output is set to 0. When the load_cnt signal is low, the input data is assigned to the output. When count_enb is high, counting occurs at every positive edge of the clock. updn_cnt controls whether the counter counts up or down.
How to test
Set signals and confirm counting.
External hardware
7-segment disply and driver, resistors.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | data_in[0] | data_out[0] | |
| 1 | data_in[1] | data_out[1] | |
| 2 | data_in[2] | data_out[2] | |
| 3 | rst_ | ||
| 4 | ld_cnt | ||
| 5 | updn_cnt | ||
| 6 | count_enb | ||
| 7 |