217 serv - Serial RISCV CPU
217 : serv - Serial RISCV CPU
- Author: Greg Davill
- Description: An award winning RISCV CPU!
- GitHub repository
- Open in 3D viewer
- Clock: 0 Hz
How it works
This project contains a 96bit serial scanchain, and the core of the serv CPU. Signals present on the scanchain are a wishobne bus and the native registerfile interface. As there is not enough room inside the TinyTapeout project area to fit RAM/registerfiles these have to be implemented externally. In theory just a bit of custom code running on caravel will be enough to get the serv core running.
How to test
tbd
External hardware
tbd
IO
| # | Input | Output |
|---|---|---|
| 0 | clock | segment a |
| 1 | reset | segment b |
| 2 | segment c | |
| 3 | segment d | |
| 4 | segment e | |
| 5 | segment f | |
| 6 | segment g | |
| 7 |