Tiny Tapeout > Tiny Tapeout Chips > Tiny Tapeout SKY 26b

Tiny Tapeout SKY 26b

Design details

Chip map

All projects

Address	Title	Author	Description
0	Chip ROM	Uri Shaked	ROM with information about the chip
1	Tiny Tapeout Factory Test	Tiny Tapeout	Factory test module
3	KK Zuzel Motocross IEEE	Krzysztof Kluczek	A motor track racing game for up to 4 players, each using only one button.
5	4-Bit High-Security Password System (IEEE)	mustafa hussain	4-bit password security system using logic gates. Grants access for the correct code and triggers a persistent alarm for the trap code (1111). Uses an SR latch so the buzzer and LED stay ON even if inputs change, requiring manual reset. Demonstrates combinational and sequential logic in hardware security.
7	4 bit unlock (IEEE)	Genuka Giyon	4 bit unlocking system with correct password as(1010)
9	Guess the Number Game - IEEE OpenSilicon Bootcamp	Maria Emilia Cueva	Guessing game with 3 attempts and hints.
11	A simple 8-bit square root calculator.	Chiranjeet Bhattacharjee, Himadri Ghosh, Aditya Panigrahi, Debaditya Dasgupta, Subir Kr. Maity	Calculates the square root of an 8-bit unsigned integer using the non-restoring algorithm. The output is provided in Q4.4 fixed-point format, allowing for fractional precision.
13	tt_um_scisneros29_BCR	Juan, Cris y Santi	Banco (BCR) de registros
15	tt_um_DlynchR_spi_display	Denzel	SPI slave -> 3-digit 7-segment display
32	Chipping Away to Learn about The Chips	Zhi Ling	v1 logo bouncing
33	ascii_typewriter	Au Kai Zhe	Displaying the sentence As above, so below with typewriter effect
34	Bomberman	Sylvia Ker	2 Player Mini Bomberman
35	Finite Field AES S-box	Prathiba	Composite field Lightweight S-box implementation
37	Hamming(7,4) Encoder/Decoder	Joseph Santhosh K,Noel Jose, Tinu P Mathew, Abhinav Kuruvila, Sahil K	Single-bit error correcting Hamming(7,4) encoder and decoder.
38	SHaRC VGA Demo	James Ashie Kotey, SHaRC	SHaRC Logo VGA Demo
39	Shiftregister Challenge 40 Bit	Thorsten Knoll	The design is a 40 bit shiftregister with a hardcoded 40 bit number. The challenge is to find the correct 40 bit to enable the output to high. With all other numbers the output will be low.
41	Digital Stopwatch with LAP mode	Nano CNMN IPN	Digital stopwatch in Verilog with Start/Stop and Lap functions, showing hundredths and seconds on a multiplexed 7-segment display.
42	Recursive Rectangles	bleeptrack	generative pattern creatures using silicon cross stitch
43	inec_voting	Ebube	inec voting
45	Mini TPU v2	Miloudi Adel Hani and Sotehi Yacine and Yassine Hamzi and Talhi Mehdi Boudraa Nadjib and Dennis Du and Rick Gao	The systolic array for the Mini TPU v2 in Tiny Tapeout is a compact, parallel processing architecture optimized for matrix multiplications, utilizing a 3x3 array of processing elements to efficiently perform multiply-accumulate (MAC) operations., while the input and wheights can be fetched externally through SPI, built with funding from IEEE
46	MAW Bird Shooter VGA Game	Marc-Andre	A fully synthesized single-player bird-shooting arcade game on a Tiny Tapeout ASIC driving a 640x480 60 Hz VGA display: move a crosshair with four directional buttons and press SHOOT to hit a wandering animated bird within 10 shots, with HIT/MISS overlays, a shot counter, and win/lose screens.
47	TTSKY-SPSRAM-legacy-direct	Staf Verhaegen	Sky130 single port SRAM with pins connected directly to TT tile pins and legacy layout bit cell.
65	Tiny Tapeout : Lock system v2 (IEEE)	Sadeeptha Palihawadana	4 digit lock system
67	(IEEE) rv32i RISC-V ALU	Ahmed Mustakim — UCF EEE-5390C	Full 32-bit RISC-V ALU implementing ADD SUB AND OR XOR SLL SRL SRA SLT SLTU. Part of rv32imsu SoC designed in Synopsys ICC2 on sky130A at UCF.
69	The Siliconimist Chip1	The Siliconimist - John Cole	The Siliconimist Chip1 is a 1x1 tile ASIC that is a simple hello world project.
71	Smartcard PLL Clock Generator	William Anthony	Enable-controlled PLL clock generator model for smartcard timing experiments
73	Sigma-Delta Bitstream ADC (8-bit)	William Anthony	Enable-controlled 1-bit sigma-delta decimator ADC with gain and offset trim
75	TTSKY26A BCD to 7-Segment Decoder	William Anthony	Tiny Tapeout HEX-to-7-segment decoder (0-9,A,b,C,d,e,F) with blank, lamp-test, decimal-point, and active-low mode support.
77	SumItUp Hardware Thread (18-341)	Bill Nace	Implementation of the SumItUp thread from CMU's 18-341 course.
79	dma_multi_channel	Sharanya	Design of a Tiny DMA controller for memory to memory copy
128	Secret Guessing Game	Enrico Goller	Guessing a password which can be set new for each game
129	Chasey	Yansi Foong	Control a player in a maze to escape the ghost
130	IEEE_UART_TX_Module	LIM ZING	Simple uart TX module
131	8-bit Accumulator CPU SoC	Fidel Makatia	8-bit accumulator microcontroller with 33-instruction ISA, 32-word ROM, 32-byte RAM, hardware stack, UART TX, and timer/counter
132	SPI Memory Test	James Ashie Kotey	SPI RAM reader with VGA timing output
133	IEEE MBIST & ECC for RAM 8x32	Dat Dinh Trong	This is MBIST and ECC on 8x32 data RAM
134	Onchip-UIS CLK Frequency Divider	Ramon Sarmiento	Generates several frequency clock signals from a user-selected M module
135	Basic8 CPU	SalihOmerOngun	8-bit minimal CPU with 8 registers, ALU, branches and JAL
136	3Bit_yALU_IEEE_V2	Yousuf SH Mohammad	A 3 bit ALU (multiplication, division, subtraction). It also allows for the switches, RST, and clock signals to pass to the output.
137	18244-s26-tiny-nn	siena	a tiny NN that determines if a point is inside or outside a circle boundary
138	Onchip-UIS 4-bit Ripple Carry Adder	Nestor Matajira	A structural 4-bit Ripple Carry Adder using half and full adders.
139	TinyFarm	Erika Ramirez	18644 Final Project
140	Everton - Tiny Tapeout Workshop LC26	Everton Ribeiro	8-Channel LED Pattern Sequencer
141	TinyPomodoro	Amelia Lobo	Pomodoro Timer and Date & Time Clock
142	Tiny Tapeout Hackaday 2026	Thomas Hornoff	TT Hackaday Lecco 2026
143	OCPU	Ayan A.	PLL-based OverClockable CPU
160	16 bit Galois LFSR based Random number generator-IEEE	Subir Maity, Jitendra Kr. Das	Random no generator using LFSR with user selectable 32 different polynomial
162	IEEE Happy Birthday Detector	Team Kanyarashi	Transmits a serial bit stream and detects a 9-bit birthday pattern (March 7), counting and displaying hits per second on a 7-segment display
164	IEEE Multi-Mode Procedural VGA Graphics Engine	Kannan S J	Procedural VGA graphics engine with multiple real-time modes using arithmetic-only rendering.
166	a tour-in the haunted house	Amine AND AMEL	this games u will be playing as a little child
168	Programmable Clock Generator	Basil Mathews Biju, Rohn Eldho and Adithyan A	clock genrator
170	TinyCrypto-8	Team Apex	An 8-Bit Pipelined ALU with Hardware Cryptography
172	Configurable 8-bit Streaming DSP Core	Logic Loopers	A 4-mode streaming DSP core implementing 4-tap FIR and IIR filtering with dynamic scaling and saturation protection.
174	Full Adder: Binary Addition Circuit	Felix Onsongo	This full adder circuit adds three binary inputs (A, B, and Carry-in) to produce a Sum and Carry-out. Built with standard logic gates, it serves as a core component for arithmetic operations in digital systems.
192	Logic-Locked 5-Bit RNGy	Ragib	A 5-bit LFSR-based random number generator with key-based logic locking, bounded output, and a 7-segment display for the rightmost decimal digit.
193	Analog design	Zedulo	A tri 2 -input AND gate (7408 compatible) and an SR Latch
194	TRI-1 Phi — Trinity φ-anchor 1×1 Lucas POST + CLARA Gap-4	Dmitrii Vasilev	Smallest SKU of the TRI-1 Triad (φ-anchor / e-engine / γ-surface) — a single-tile Trinity GF16(2^4) ternary dot4 MAC with enhanced safety. On reset the chip drives the canonical dot4(1.0,2.0,3.0,4.0) = 0x47C0 directly onto {uio_out, uo_out}, matching the same constant emitted by e-engine (tt-trinity-euler) and γ-surface (tt-trinity-gamma). This is the cross-die anchor for the TG-TRIAD-X ledger (PhD Theorem 36.1). Enhanced modules: phi_anchor_post (Lucas L₂..L₇ POST proving φ²+φ⁻²=3), lucas_rom (addressable L_n host probe), hwrng_lfsr (die-unique nonce), restraint_ctrl (CLARA Gap-4 bounded rationality), sacred_constants_rom (75 PhD constants), crown47_rom (Trinity constants), friend/foe handshake. v1.0.0: GF4-GF256 formats, quantizers (Int4/Int8/NF4/FP8/Posit16), sacred opcodes (0xDF, 0xE1-0xED), power modules (AVS-96, FBB, Purkinje). R-SI-1: zero `*` operators in synthesisable RTL. Anchor: phi^2 + phi^-2 = 3. DOI: 10.5281/zenodo.19227877. TOPS/W: 75 baseline, 405 with AVS-96 (5.4× boost).
195	IEEE Tiny 8bit CPU	Korichi Aymene, Bouyahiaoui Hadjer, Boubraa Nadjib	A tiny compact 8-bit 4 general register CPU with 16 instructions
196	ulogic_analyzer	lujji	useless logic analyzer
197	UART Smart I/O Hub	NAVEEN KUMAAR S	IEEE SNK_UART-controlled 64-channel PWM hub with banked outputs, internal modulation engine, ALU datapath, and sequencer.
198	127-stage Coarse-Tapped ADPLL	Catalin Lazar	A lower-frequency All-Digital PLL featuring a 127-stage tapped structural ring oscillator targeting 125MHz midpoint locking loops on SkyWater 130nm.
199	VGA Screensaver with embedded bitmap ROM	Uri Shaked	64x64x6bpp Tiny Tapeout Logo bouncing around the screen (640x480, TinyVGA Pmod)
200	IEEE \| 24-Bit Serial Fixed-Point Binary Divider	Miguel Angel Tobón Morales	Serial divider implemented in Verilog for 24-bit fixed-point numbers with 23 fractional bits, capable of performing normalized binary divisions within an approximate range of 0 to 1.9999999.
201	IEE EML Gate	Taouinar Abdelbasset & Sidahmed Hamdad	Q6.14 fixed-point EML operator eml(x,y)=exp(x)-ln(y) with SPI interface
202	Swarm Microrobot Drug Delivery FSM	An Bui	Finite state machine for clot detection, swarm communication, drug release, and motor control
203	2x2 Systolic Array TPU	PFW Tiny Tapeout Team	A 2x2 systolic-array Tensor Processing Unit that performs signed 8-bit matrix multiplication with 16-bit accumulation, optional fused transpose, and ReLU activation. Pipelined streaming allows overlapped input/output.
204	TTSKY-SPSRAM-direct-librelane	Staf Verhaegen	Sky130 single port SRAM with pins connected directly to TT tile pins using librelane.
205	4x4 BitNet b1.58 Matrix Multiply Accelerator	siriboi	SPI-controlled 4x4 W1.58A8 matrix multiply accelerator (BitNet b1.58): uint8 activations x ternary {-1,0,+1} weights, multiplier-free PE-parallel MAC
206	tinyCGRA 2x2	rikutoide	2x2 tiny CGRA array with serial configuration
207	Automation Laboratory Logo with author Image	Belkacem BENADDA	Use the VGA interface to display either the laboratory Logo or the Author Image
227	Custom 3 by 3 Systolic Array	Carter Brady	This is a 3 by 3 systolic array with 4 bit inputs that performs matrix multiplication.
229	Floating-bulk-test-2	Rogelio Garzon. Felipe Salinas. Mireyda Arangure. Cesar Leal. Alejandra Lopez. Brenda Lopez.	Punch through current test
233	Bio-SSG	Jose Abel Rodriguez Soto, Alvaro Gonzalo Soto Renteria	Sinusoidal Signal Generator for Bio-Application
238	Tiny FABulous FPGA	Leo Moser	A tiny FABulous FPGA fabric, ready for use with Yosys and nextpnr.
239	mini mosbius	andrew kang	a mosbius style chip in a 3x2 tt slot
261	Tile Growth Simulator	Noah Wilmot	Simulates random tile growth on a 16x16 LED Matrix
263	Oscillating Bones	Uri Shaked	A stylish ring oscillator built from SkullFET transistors
265	Pseudo-PTAT cell based bandgap reference	Istvan Kovacs	Simple bandgap reference voltage generator based on the pseudo-PTAT current generator with enable gated startup included.
267	brainamp-ac-coupled-lna	Rahul Bhagwat	AC Coupled Low Noise Amplifier for a brain computer interface
271	UART_Controller	Preetish	Programmable through UART, I can choose between Analog circuits like Inverters
288	Flappy VGA	Akul Singh	A TinyTapeout implementation of a simple Flappy Bird-style VGA game with button inputs and RGB/sync outputs.
289	AoC Hardcaml Coprocessor	hackin7	Advent of Code day-1 style position coprocessor (Hardcaml), with byte-serial TT wrapper
290	tiny OoO CPU	Amin Hong	Small out-of-order CPU with instruction queue, RAT, ROB, and reservation stations
291	8-bit counter	Iwyil	Simple 8-bit counter with set-able counting amount
292	Slot Machine	Edward Lei	Spins 3 slots
293	Claire's first Wokwi design	Claire Elliott	Claire's first Wokwi design
294	AXI4-Lite Slave Register Demo	jenny82121027	Tiny Tapeout AXI4-Lite slave wrapper with a read-only ID register, 32 registers, and a 16-bit readback path on the bidirectional pins.
295	Daniel's first chip (Tiny Tapeout)	Daniel Petkovic	Daniels first chip
296	TinyDMA-2C	Andrew Kim	Two-channel byte DMA engine using external SPI PSRAM
297	TinyTapeout_Hackaday_Daniel	Daniel	Test
298	Tiny Rainbow Snake Game	Lilly Das	The snake game you know and love, but tiny and rainbow.
299	Tiny Tapeout Template Copy	Patryk Ankudowicz	asd
300	Tiny3D	Kevin Qian	The smallest ever 3D graphics engine
301	Tiny Tapetest	Ivan Hernandez	16b counter
302	Drone Flight Controller	Kyle Minihan	A simple flight controller for a quadcopter drone.
303	Tiny Tapeout Run1	Ricardo	one-two
321	Cordic-based Math processor-IEEE	Subir Maity, Jitendra Kr. Das	CORDIC Implementation of Sine and Cosine function
323	Mines live or die	Shreyes, Marcos, Michael	Live or die game.
325	Multi-Mode Sensor Signal Processor	AG1- Ghani Lab - Emirates Chip Competence	A multi-mode digital signal processing unit supporting filtering, accumulation, edge detection, and nonlinear transformation.
327	Heat Stress Alert ASIC	AG3-Ghani Lab -Emirates Chip Competence	Low-cost digital heat stress detection system using pulse-based input for wearable or environmental monitoring
329	Water Quality Classifier Core	AG1 - Ghani Lab - Emirates Chips Competence	Low-cost ASIC for water quality classification using signal behavior analysis
331	DDS Waveform Generator - IEEE	Daniel Roberto Garcia Miranda	Programmable DDS waveform generator with multiple waveforms, frequency and amplitude control
333	UART - Controlled Frecuency Meter & Timer - IEEE	Richard Alfredo Tarqui Mamani & Gustavo Ismael Chavez Mamani	Frequency meter, pulse counter, and programmable timer controlled via UART at 115200 baud.
335	IEEE PONG IPORRE VGA	RODRIGO MIGUEL IPORRE COCA	IT'S A PONG GAME WITH A SCORE COUNTER
416	tt_um_Nay0805_detector_de_patrones_generados_aleatoreamente	NK	comparador
418	Programmable Clock Router (IEEE)	AISWARYA VM , GAUTHAM P NAIR , LAKSHMI NAIR	8-channel programmable clock divider using a 16-bit counter and configurable routing
420	A simple 8-bit RISC-V style CPU	Subir Maity, Jitendra Das	A simple 8 bit RISC-V style CPU with basic functionality. This cou does not contain any instruction memory. Intruction code is applied externally via switches or via MCU or FPGA
422	Hackerspace logo IEEE	Jakub Rachoń	Hs3 logo displayed via VGA port on 640x480
424	SUBLEQ CPU IEEE	Touka Szulc	A type of OISC (One Instruction Set Computer).
426	Floppy LIGHT	Absygen	Floppy bird with logo LIGHT
428	BDF1000 Line folower	Belkacem BENADDA	a logic circuit and PI controler for the BFD1000 Line follower sensor dedicated to tinytapout SKY26a
430	Space-Time Waves and Filaments	AlephNaNsea	A generative VGA hardware video synthesizer featuring cosmic webs, rolling ocean waves, and fractal patterns.
448	TTSKY26A Neural Network - LSTM Wake Word Detector	William Anthony	8-bit quantized LSTM for real-time 'NYALA' (Light On) wake word detection. Privacy-first smart home voice controller.
450	test	brendtam	does something
452	(IEEE) rv32i RISC-V Branch Condition Unit	Ahmed Mustakim — UCF EEE-5390C	RISC-V rv32i branch condition evaluator implementing all six branch instructions BEQ BNE BLT BGE BLTU BGEU. Companion to the rv32i ALU tile. Both are components of a complete rv32imsu RISC-V SoC designed in Synopsys DC Shell and ICC2 on sky130A 130nm PDK at UCF EEE-5390C.
454	8-bit Tiny ALU	Joseph Santhosh	8-bit arithmetic logic unit supporting arithmetic, logic, and shift operations with status flags.
456	C0haotic RNG	onrkrts	Programmable chaotic random number generator based on a 3D chaotic map
458	IEEE IC Bootcamp Khalifa University	Nuzhat, Ayesha and Umamah	This is a 3-bit reversible comparator
460	2x2 Systolic Array Matrix Multiplier	Roshan Tripathy, Dr. Amit Bakshi, Ashmit Avash	2x2 signed 4-bit systolic array matrix multiplier with 9-bit accumulators, overflow detection, sign reconstruction, and manual step mode
462	IEEE CRC_FIFO: CRC-32 Engine with 8-Byte FIFO and VGA Displa	Jorge Luis Chuquimia Parra	Hardware CRC-32 engine (IEEE 802.3, 0xEDB88320) with 8-byte FIFO, 1-bit-per-cycle serial processing, bidirectional register read interface, interrupt output, and real-time VGA display showing FIFO occupancy bar, FSM state, and all 32 CRC bits across two grid rows. Single clock domain.
463	ASCON-CXOF128 Hash-Chain Accelerator	Dr. Mohamed El-Hadedy	ASCON-CXOF128 (NIST SP 800-232) hardware accelerator with hash-chain wrapper for iterative hashing in hash-based signature schemes (SLH-DSA, LMS, XMSS). UART-framed protocol with single-shot and n-iteration chain modes.
482	Tiny_Tapeout_Launch_Controller	Eric Pearson	Launch control chip
484	LDO Regulator Skywater 130nm	Engineer of CTW	Low Drop Out Regulator with Supply Independent Current Circuit
486	Onchip-UIS Ring Oscillators for Aging	Ramon Sarmiento and Jorge Angarita and Jeison Acevedo and Daniel Barrios and Nicolas Orcasitas and Juan S. Moya	13-stage Ring Oscillator for aging analysis (BTI/HCI)
488	SKY130 Spiking Neuron	Abdulkarim Alorf, Tomohisa Kawakami	A compact analog spiking neuron
494	tnt's variant of SKY130 mini-MOSbius	Sylvain Munaut	Alternative layout for Andrew Kang's mini-MOSbius for SKY130 TinyTapeout
512	Tetrahedral Oscillator	Juvenal Romero Pedraza, Gael Gabino Diaz Ojeda, Mario Ranferi Romero Salgado.	Tetrahedral oscillator based on coupled CMOS inverter pairs with capacitive load tuning.
515	raycaster	Abhinav Puthran	Wolfenstein-style raycaster 3D maze rendering in 640x480 VGA at 25MH
517	bandgap-ptat	rcyaon	1.2V Brokaw bandgap voltage reference with PTAT temperature readout
519	sky130 Bandgap Reference	Guruprasad	Bandgap reference (~0.9V) with analog VREF output
520	CNN4IC — Convolutional Neural Network (CNN) for Image Classification on Chip (IEEE)	Jacobo Morales, Hernando Diaz, Martín Calderón, Daniel Pedraza, Mateo Fernandez. Mentors: Juan S Moya, Fredy Segura, Alba Avila	CNN accelerator that classifies 10x10 images using two 5x5 kernels via SPI interface
521	tt26b-Babies-First-LDO	Devan Comes	0.1-4mA, 1.8 to 1.4V LDO
522	5 GHz RF-DC Rectifier	Carlos Knebel	Differential RF-DC rectifier in Sky130 for passive RFID / RF energy harvesting experiments.
523	ttsky26b-ramp-adc	Christian Zingl	2-channel ramp ADC
524	Operational Transconductance Amplifier	Santino pasquale	Outputs current porportional to input voltage
525	CSRO with 8-bit DAC	Luca Maddison	Voltage controlled ring oscillator with 8-bit DAC and analog input
526	STDCELL_LDO	ABNER JOSE PARRA HERNANDEZ	LOW DROPOUT VOLTAGE REGULATOR
527	IEEE Multi-Stage Configurable Ring Oscillator	Nemalipuri Rajkamal	Analog clock generation unit with voltage-controlled MUX routing between 3, 5, and 7-stage ring oscillators on the Sky130 process.
545	INTERCAL ALU	Rebecca G. Bettencourt	An ALU for the five operators of the INTERCAL programming language.
547	Hardware UTF Encoder/Decoder	Rebecca G. Bettencourt	Converts Unicode code points between UTF-8, UTF-16, and UTF-32.
549	Onchip-UIS Collatz Conjecture	Sergio Sebastian Oliveros Sepulveda	A circuit that computes the Collatz orbit
551	Onchip-UIS PWM Generator	Daniel Barrios	Generates a PWM signal with a duty cycle that can be varied with inputs pins
553	Universal Binary to Segment Decoder	Rebecca G. Bettencourt	Decodes various binary codes to various segmented displays.
555	Onchip-UIS Traffic Light	Jorge Eduardo Angarita Pérez	Traffic light control
557	Nano-Bnn-Accelerator	Giorgos Fragkoulis	A regular binary network accelerator for 1x1 tile Z2A
558	TRI-1 Euler — Trinity e-engine 8×2 SUPER-CROWN + 10 CLARA Gaps	Dmitrii Vasilev · Trinity Stack	TRI-1 Euler is the e-engine SKU (Trinity TRI-NET sacred-constant triplet: phi-anchor / e-engine / gamma-surface) of the TRI-1 Triad submitted to TTSKY26b (siblings: tt-trinity-phi 1x1 anchor, tt-trinity-gamma 8x4 surface). 8x2 tiles = 16 GF16 cells + full SUPER-CROWN modules + 10 DARPA CLARA AI safety gaps + D2D holo mesh. v1.0.0: GF4-GF256 formats, quantizers (Int4/Int8/NF4/FP8/Posit16), sacred opcodes (0xDF, 0xE1-0xED), power modules (AVS-96, FBB, Purkinje). TOPS/W: 75 baseline, 405 with AVS-96 (5.4× boost). SUPER-CROWN modules (18): - phi_anchor_post + lucas_rom (proves phi^2 + phi^-2 = 3 via Lucas) - vsa_matmul_8x8 + vsa_matmul_16x16 (ternary VSA, JEPA-T tier) - bitnet_encoder (BitNet b1.58 ternary MLP) - bpb_counter (on-chip cross-entropy/BPB) - blake3_anchor + multi_tile_receipt + crc32_receipt (G4 DePIN signing) - alu9_decoder (9-instruction Trinity ternary ALU, t27 ISA) - ring27_memory (27-cell 3^3 ternary memory, Coptic) - hwrng_lfsr (die-unique nonce) - phi_pll_div (phi-PLL fractional divider) - wishbone_full + wb_status_reg (host interface) - trinity_master_fsm (packet master) - gf16_dot4/8/sparse (ternary arithmetic) - gf16_popcount (population count) DARPA CLARA AI Safety Gaps (10): - Gap-1 redteam_filter (adversarial detection) - Gap-2 k3_alu (Kleene K3 ternary ALU, TA1.1) - Gap-3 datalog_engine_mini (forward-chain Datalog) - Gap-4 restraint_ctrl (bounded rationality, TA1.4) - Gap-5 explainability_unit (proof-trace emitter, TA1.2) - Gap-6 asp_solver_mini (ASP solver with NAF) - Gap-7 composition_kernel (orchestrator Gap-3/4/5) - Gap-8 proof_trace_writer (on-chip audit receipt) - Gap-9 sat_solver_mini (DPLL SAT solver) - Gap-10 audit_log_ring_buffer (64-entry event log) D2D Network: - d2d_holo_mesh (4-port N/E/S/W router, LAYER-FROZEN gate per PhD Thm 36.1 R18) Anchor: phi^2 + phi^-2 = 3 (Trinity algebraic identity). DOI: 10.5281/zenodo.19227877. FPGA-validated at 323 MHz on XC7A100T; silicon target 50 MHz @ SKY130A. Ten chip-market differentiators (no competitor has all ten — Hailo-8, MediaTek D9400 NPU890, QC Cloud AI 100 Ultra, Axelera Metis M.2, Google Coral Edge TPU all miss at least two): (1) native ternary {-1,0,+1} MAC silicon; (2) on-chip BLAKE3 receipt signer (G4 DePIN); (3) POST self-test via phi^2 + phi^-2 = 3 Lucas chain; (4) 0 DSP / 0 new `*` in synthesisable RTL (R-SI-1); (5) BitNet b1.58-style ternary MLP encoder on-chip; (6) RING27 27-cell ternary memory (3^3); (7) Trinity 9-instruction ternary ALU (t27 ISA preview); (8) on-chip BPB / cross-entropy counter; (9) Apache-2.0 + fully open PDK (SKY130A); (10) DOI-anchored + Coq-verified provenance — t27/trios-coq carries 297 Qed and 141 Admitted at submission (the older "84 theorems" figure is folklore predating the 2026-05-12 consolidation and is explicitly retired here). Anchor: phi^2 + phi^-2 = 3 (Trinity algebraic identity). DOI: 10.5281/zenodo.19227877. PhD chapter: trios docs/phd/chapters/flos_70.tex (Ch. 36 TRI-1 Triad, Theorem 36.1 TG-TRIAD-X — cross-die ledger determinism). Provenance: trinity-fpga#19 (FPGA EPIC), trinity-fpga#49 (L-DPC7 TRI-1 Triad EPIC), trios assertions/igla_assertions.json (R-SI compliance), tt-trinity-gf16 docs/architecture/TRI_NET_SHUTTLE_TRIAD.md (canonical Triad architecture spec). Defense: 2026-06-15.
559	ALU8 Serial (IEEE)	Jonathan Cardona Ramírez	8-bit serial-in ALU with parallel result and done, zero, negative/sign, carry/borrow, overflow flags (ADD, SUB, AND, OR, XOR, NOT).
577	Open Silicon 2026: SKY26a Submission - Chapter Logo	IEEE IES-IPS Philippine Chapter	Submission #1 to the SKY26a shuttle for Open Silicon workshop
579	IEEE Mitchell-s_Approximation_based_EML	Boussaa Youcef, Korichi Aymene, Bouyahiaoui Hadjer	Multiplier-less EML gate using Mitchell’s approximation for energy-efficient transcendental processing in ASICs.
581	Digitally Controlled Oscillator	Sollys Le - PVC	The digitally controlled oscillator (DCO) generates a frequency-adjustable clock signal based on an 8-bit control input.
583	Ford Thunderbird Rearlights Controller - IEEE OpenSilicon Bootcamp	Juan Fernando Posso & Pierina Miraba	The circuit implements a sequential rear-light controller inspired by the Ford Thunderbird, using a 2-bit counter to generate timing states. A controller and decoders convert these states into progressive left and right light patterns based on the input signal.
585	IEEE_CPU with SPI program load and internal execution	Luis Javier	8-bit CPU that loads 16-bit instructions over SPI into internal program memory and then executes them autonomously. Final stable version uses 10 instruction slots and an enriched ISA.
587	IEEEcoffee_chip	Juan Pablo Tabares Cardona	El Coffee Chip es un sistema de clasificación de granos de café implementado directamente en silicio (ASIC) mediante el proceso de fabricación TinyTapeout (Sky130). El diseño utiliza lógica digital de alta velocidad para procesar señales de frecuencia provenientes de un sensor de color (como el TCS3200), permitiendo categorizar granos en tres estados: Inmaduro, Óptimo y Pasado.
589	Philippine IC Design Boot Camp 2026!	Alexander Co abad	Philippine IC Design Boot Camp 2026 Matrix-style display based on VGA Glyph by James Ross https://tinytapeout.com/chips/ttsky25a/tt_um_vga_glyph_mode
591	IEEE 7-bit ALU - Serial Input / Parallel Output	Sharif Obando	7-bit ALU with LSB-first serial input and 8-bit parallel output. Supports ADD, AND, OR, XOR and SUB. Protocol: 7 bits operand A + 7 bits operand B per clock edge (14 rising edges total). The opcode op[2:0] is a stable parallel input on ui_in[3:1]. Done signal on uio[0] pulses high for exactly one clock cycle to indicate end of operation.
672	Galvantronix, DLSU, and me!	Chico Andre G. Olaguer	VGA chip that features DLSU animations, Hilbert Curves, Mazes, and the Galvantronix Logo.
674	8-bit Multiply-Accumulate (MAC) with 2-Cycle Serial Interface	Lê Hồng Phúc	An 8×8→16-bit multiply-accumulate unit with 2-cycle 8-bit serial interface, supporting signed/unsigned operations with overflow detection and clear functionality
676	Open Silicon 2026: SKY26a Submission - Chapter Logo	IEEE IES-IPS Philippine Chapter	Submission #1 to the SKY26a shuttle for Open Silicon workshop
678	IEEE Letters Screensaver	Raphael Garcia	IEEE Letters Screensaver for VGA. Code made using Gemini
680	PSI Open IC 2026	S.Hajibaba G.Theidel J.Zhang	Simple UART Transmitter
682	FULL SUBTRACTOR	Draoui Yacine and Mohammed Ali	full subtractor simple design
684	Sunblock Holiday	Lauren Riddiford	Puzzle allowing 2 and only 2 holidays (with an extra sunscreen option)
686	Digital Clock!	Alexander Co Abad	Digital Clock
704	IEEE Logic Locked Reversible 2-Bit ALU	Fawaz Ahmed	Secure 2-Bit Reversible ALU with bijective mapping and Fredkin gate logic locking
706	ALU 7 Bits	Miguel Angel Tobón Morales	Unidad aritmético-lógica (ALU) de 7 bits que trabaja de forma secuencial con entrada serial y salida paralela.
707	AES S-Box / PRESENT	xeniarose	AES forward S-Box circuits, and also PRESENT
708	Onchip-UIS 8-bit ALU with Status Flags	Nicolas Orcasitas	A 8-bit ALU with registered inputs, 8 arithmetic/logic operations, and 8 configurable status flags.
710	IEEE Open-silicon 2026 x NITHUB: Fluid Level Detector and Controller	Ore-Oluwa Oluwatosin, Akeem Jr Odebiyi, Victor Awofegha, Ogunlowo Oluwasegunfunmi, Saka Suliat	IEEE Division 1 Open Silicon Initiative Tapeout Project, this is a 4-state FSM that drives a water pump from two level sensors, with an impossible-state error flag.
711	Systolic VGA Visualizer	siriboi	4x4 ternary systolic-array demo with 640x480 VGA output. The array result matrix is rendered directly as a 4x4 fullscreen heatmap.
712	First Silicon	Matthew Schubert	.
714	Tiny Tapeout Template - PJ v2	Paul Johan de Voogd	Noob example
715	TRON: Light Cycles game with VGA support (IEEE)	Jacombo Morales, Hernando Díaz	TRON: Light Cycles 2 player game implemented on chip using VGA output
716	Silicon Artwork	Kristaps Jurkans	Hatsune Miku and Juno Teo Minh in silicon!
717	Hardware Triangle Rasterizer with VGA Output	Pauline Zhu	Edge-equation triangle rasterizer rendering filled triangles to a 256x256 VGA viewport at 640x480@60Hz
718	tiny-tapeout-2026-05-16	Kay	Required
719	Reaction Time Game	evstorms	Multiplayer reaction time game with VGA display output (640x480), supporting Classic and Target Match modes
750	TRI-1 Gamma — MAX-TRUE NEUROMORPHIC FLAGSHIP 32-tile 8-column	Dmitrii Vasilev	MAX-TRUE NEUROMORPHIC FLAGSHIP SKU of the TRI-1 Triad (TTSKY26b). 32 tiles = 8x4 TT footprint. Architecture: 8 cortical columns (cortical_column.v — LIF leaky-integrate-and-fire dynamics with 8-bit membrane potential, BitNet b1.58 ternary MLP hidden layer, GF16 dot4 input projection, sparse PE accumulator; ~500 cells/column = ~4100 total) + 20-PE GF16 mesh (1x trinity_quad_mesh 16 PE + 1x trinity_mesh_2x2 4 PE) + 24 SUPER-CROWN modules (phi_anchor_post, lucas_rom x7, vsa_matmul_8x8, vsa_matmul_16x16, bitnet_encoder, bpb_counter, blake3_anchor, multi_tile_receipt, crc32_receipt, alu9_decoder, ring27_memory, hwrng_lfsr, phi_pll_div, wb_status_reg, wishbone_full, trinity_master_fsm, trinity_mesh_2x2, gf16_dot4, plus 6 PhD-anchored monitors: cassini_post, plrm_counter, bpb_lower_bound_guard, nca_entropy_monitor, strobe_seed_guard, phi_distance_oracle) + D2D holo mesh 4-port N/E/S/W router (d2d_holo_mesh.v — adapted from tt-trinity-holo TTSKY26c lineage; uio[3:0]=TX, uio[7:4]=RX inputs; LAYER-FROZEN gate on w_tx per PhD Theorem 36.1 R18) + full Crown47 ROM (crown47_rom + crown47_rom_8bit) + TRI NET friend/foe handshake (GAMMA anchor 8'h93) + FHRR holo_lut_pe (VSA binding, Glava 32). v1.0.0 enhancements: GF4/GF8/GF12/GF16/GF20/GF24/GF32/GF64/GF128/GF256 formats, quantizers (Int4/Int8/NF4/FP8_E4M3/FP8_E5M2/Posit16), sacred opcodes (0xDF LUT_LOOKUP, 0xE1 SPARSE_SKIP, 0xE3 LUT_NPU, 0xE5 SUBTH_CLK, 0xE6 HOLO_MUX_X4, 0xE7 DFS_GATE, 0xE8 SPARSE_SKIP2, 0xE9 STOCH_ROUND, 0xEA NULL_PE, 0xEB SPEC_EXIT, 0xEC DROWSY_RET), power modules (AVS-48/96, FBB, Purkinje thermal). TOPS/W: 75 baseline, 405 with AVS-96. TG-TRIAD-X canonical anchor 0x47C0 on {uio_out,uo_out} at reset (PhD Theorem 36.1, docs/phd/chapters/flos_70.tex). R-SI-1: zero NEW * operators (legacy gf16_mul grandfathered per TRI_NET_SHUTTLE_TRIAD.md Rule 2 / tt-trinity-gf16#4). Anchor: phi^2 + phi^-2 = 3. DOI: 10.5281/zenodo.19227877. tt-trinity-holo D2D lineage (TTSKY26c, 1x2, r_marker_rom.v). S-13 dual-lib: sky130_fd_sc_hd primary + sky130_fd_sc_hdll for low-activity blocks. See docs/L-DPC22-K-DUAL-LIB.md.
769	3x3 Serial Matrix Multiplier (4-bit)	Umit Anik	Serial-load 3x3 unsigned 4-bit matrix multiplier with 10-bit output (2 bytes)
770	SandSim	Alden Grover	Physics engine that simulates falling sand on a 2d plane
771	Tiny Crypto Core	Bartu Abdioglu	Lightweight 64-bit symmetric encryption/decryption demo core
772	Simple Ring Oscillator	ER	Ring Oscillator Tryout
773	ttsky-blackjack	Armağan Bi	Blackjack card game with hit/stand buttons, 7-segment display for sums, and win/lose/push LEDs
774	Analog BGR	Youssef Emad	simple Bandgap reference
775	mini_cpu	amarjay	a minimal 8-bit accumulator-based processor
776	4-Stage Differential Ring VCO	Adithya Selvakumar	A current-controlled 4-stage differential ring VCO with buffered quadrature outputs.
777	IEEE Multi-Channel PWM Controller	pvc	Multi-Channel PWM controller with configurable frequency, dead-time insertion, phase offset, and fault protection, configured via SPI
778	Onchip-UIS 3-bit Trimmed 1.2V BandGap	Jeison Acevedo and Ramon Sarmiento and Camilo Estevez	A 1.2V CMOS Bandgap Reference featuring a 3-bit resistor trimming network for PVT variation compensation.
779	Bypass Universal	Joshua Cervantes	Gestor de Bypass Universal
780	capless LDO regulator with 51.1dB PSRR at 100kHz	Dzaki Andriansyah	low dropout regulator with 1.27V output
781	IEEE_UPP_Garage unit control	Sadrac Santiago, Carlos Romero and Martin Amastal	Sistema de control para controlar apertura, cierre y paro de un garage con un solo botón
782	TTSKY26a_Miller_OTA(IEEE)	Yeditepe VLSI Team	Miller OTA
783	IEEE_henon	ktri	henon map
800	Kunal ML co-processor	Kunal Ghosh	Machine learning co-processor
801	3020 Test Repo 4x4 Array Multiplier	Trent Reuben	Performs a 4x4 structural array multiplier using fulladders
802	VGA Pride	Rebecca G. Bettencourt	A VGA demo for showing pride flags
803	OneTile!	Leo Qi	This Conway's GameOfLife fits on one tile!
804	TTNN: Pre-trained BNN for 8x8 MNIST	Petros Emmanouilidis	A pre-trained Binary Neural Network for 8x8 MNIST
805	Tiny Tapeout Template Copy	Juan Manuel	Test
806	IEEE Devil Nyan Cat VGA	Daniel García	VGA Nyan Cat with synchronized audio and a real-time color mutation toggle (Devil Mode).
807	Tiny Tapeout Exercise	Brett Gibson	Simple 4-bit adder
808	IEEE VGA Charizard Flamethrower	Dat Dinh Trong	Displays the Charizard on VGA with a flamethrower animation!
809	EDS workshop 4bit adder	Jeevan	Example 2bit adder
810	VGA Screensaver with Silicon Art ROM	Uri Shaked	TinyTapeout logo bouncing around a 640x480 VGA screen, with the bitmap stored in a NOR ROM whose transistor pattern is silicon art (TinyVGA Pmod)
811	BSS UART	James Ashie Kotey, Kreesha Ramachandran, Kwashie Andoh, SHaRC	SHaRC Byte-Sized Serial UART IP Test Chip
812	4x4 Array Multiplier with VGA Visualization	Carlos Acevedo, Brock Fuller, Akshat Verma, Vance Vojslavek, Hira Memon, Ezenwa Opara, Erik Rodriguez, Samiya Qasmi, Sahil Najmal, Matthew Hodges	A structural 4×4 array multiplier using 12 full adders that displays the input operands and the resulting 8-bit product as a decimal equation on a 640×480 VGA monitor through the Tiny VGA PMOD. The designers’ initials and the Purdue Fort Wayne mascot, the mastodon, are also shown on the display. Inputs are provided through bare solder pads for direct cable connections.
813	Hardware EEPROM Wear-Leveling Controller	Olonade Kelvin	Implements the proven Start-Gap wear-leveling algorithm, the same technique used in commercial 3D-XPoint and phase-change memories, enhanced with a 2-round Feistel address scrambler for strong resistance against wear-leveling attacks. Additional features include Hamming(6,3) single-error correction on persistent state, automatic bad-block retirement, saturating wear counters, and an in-band telemetry port for monitoring.
814	tt_um_kazan_rqpu	Tarek Alhafez	RQPU v2 reversible-computing-inspired 4-bit processor with 4-phase bus and 4x4 RAM
815	SKY PLL test project	Paul Campbell	A test tile for a TT PLL 50-250MHz
833	IEEE Rule 30 Cellular Automaton VGA Display	NAVEEN KUMAAR S	Hardware implementation of Wolfram Rule 30 cellular automaton rendered on a VGA monitor.
835	authQV RISC-V CPU	ktsoupos	QSPI flash/RAM memory controller for the authQV RISC-V CPU. The CPU itself runs on a companion FPGA; this die exposes the mem_ctrl interface over a 16-phase 8-bit parallel bus.
837	3x3 Hardware Neural Network (Programmable TPU)	Vasilis Zoidis and Savvas Tzanetis	A programmable sequential 3-neuron hardware NN with 3 inputs and ReLU using a shared MAC unit.
839	16-bit MIPS Single Cycle Processor	Dimosthenis Papathanasiou , Andreas Skoufakis , Christoforos Marinopoulos	A complete 16-bit MIPS single-cycle processor that loads 16-bit instructions through the existing 8-bit Tiny Tapeout input pins
841	AUTh DMA Controller	Spyridon Vasileiou, Zafeirios Giapoutzis, Athanasios Karatzas, Zisis Katsaros, Kiriakos Kokkinos	8-bit DMA Controller for transferring data between memory and I/O device
843	IEEE Ring Oscillator PUF	Rajkamal	8-pair RO-PUF: LFSR-driven toggle FFs, 8x12-bit counter pairs, 3-state FSM
845	Nibble - 4-bit CPU	Jacob Kebaso	A minimalistic 4-bit accumulator CPU with 16 instructions and external program memory.
847	1-bit Perceptron - Hardware Neuron	Jacob Kirera	A single artificial neuron (perceptron) implemented in pure combinational logic. Four binary inputs are each multiplied by a 2-bit weight, summed in an adder tree, and compared to a configurable threshold. The neuron fires (output = 1) when the weighted sum meets or exceeds the threshold.This is the fundamental building block of every neural network — on real silicon. Weights and threshold are set live via input pins, making it fully reconfigurable without re-synthesis.
864	tt_um_sobel_threshold	Jhon Ramirez & Diana Maldonado	Grayscale, Sobel filter and thresholding.
865	PWM UART Controller	NAVEEN KUMAAR S	UART-controlled 7-channel PWM generator
866	TT ADC SQ Compare	Takaharu YAMADA	For my academic research
868	Terre VGA	Jason Xu	VGA output with moving text Bonjour Terre
870	Mini Memory Controller	Corin Cho	Designed a fake memory controller featuring request queuing, bank-row-column address decoding, and fake memory to simulate DRAM read/write behavior.
872	Tiny Laura L	Matt Venn	Set the first 4 inputs to 1010 and see an L on the 7 segment
874	PCS Lite: Asynchronous 8b10b SerDes	Jolyan Ye	A Physical Coding Sublayer (PCS) with 8b10b encoding and CDC FIFOs between 66MHz (link) and 10MHz (system) domains.
876	basic_national_anthem_buzzer	Eren Kaçmaz	Plays the Turkish National Anthem as a square-wave melody on a piezo buzzer
878	IEEE Configurable WDT	Dat Dinh Trong	A configurable WDT 32 bit
896	Moving average Digital Low pass filter (IEEE open silicon)	Aditya Panigrahi	A Moving Average Filter is a specific type of Finite Impulse Response (FIR) filter where all N coefficients are equal to 1/N. It is widely used in digital signal processing (DSP) to reduce high-frequency noise from a signal while maintaining a sharp response to step changes in the time domain
897	My First TT Demo	noaha	Displays subjectively cool graphics
898	IEEE Open-Silicon 2026: Adaptive Traffic Light Controller with Emergency Override	Anthony Ebo, Abubakar Abdulfatah, Amaechina Sinclair, Taofeek Kassim, Abdulmaleek	FSM-based two-road traffic light controller with sensor-adaptive green-phase extension and hardware emergency-vehicle priority override.
899	latchup2026-28add11	Nicholas West	playing around with PRNG in hardware!
900	IEEE Open-Silicon 2026 x NITHUB: Soil Moisture Irrigation Controller	Shadia, Elijah, Oluwatomiwa, Emmanuel, Daniel, Orobosa	An IEEE Division 1 Open Silicon Tapeout Initiative Project, this is a finite state machine that controls irrigation pump based on soil moisture levels detected by two comparators, with error handling for invalid states
901	PulseMon8	Gurtej Randhawa	8-bit pulse monitor with edge detection and compare-match logic.
902	Systolic Binary Neural Network Accelerator	Dean Foulds	V2 systolic 16-neuron BNN accelerator. XNOR dot product engine, hardware feature expansion, signed bias, balanced popcount tree. 8-cycle systolic compute reuses hardware for smaller silicon footprint.
903	Intro_VGA_Playground	rwntlpt	displays checkered pattern
904	BCD ID Wowki	Ian Briones Reyes	Circuito convertidor de 4bit BCD a display de 7 segmentos como una pequeña modificacion del conocido IC 7448, con la diferencia de que este funciona siempre con un 0 en apagado.
905	Keypad Calculator	Vidisha Chopra	A TinyTapeout keypad calculator that scans a 4x4 keypad and outputs the 8-bit calculation result.
906	Baby CPU	Ripunjay Singh, Alok Kumar Kamal	A small 8-bit CPU with 16-byte ROM/RAM and simple accumulator architecture
907	Morse Code Translator	Nancy Anderson	Translates Morse code and displays plaintext on seven-segment displays
908	IEEE_MMU_Cybertron_Logo	Au Kai Zhe, Lim Zing	Display the logo of MMU Cybertron using VGA
909	TTSKY-SPSRAM-direct	Staf Verhaegen	Sky130 single port SRAM with pins connected directly to TT tile pins.
910	SNN AFib Detector — Spiking Reservoir Computing Core	SanjayKrishna	A spiking neural network (SNN) reservoir computing chip that detects atrial fibrillation and asystole in real time from R-peak timing pulses, using 11 LIF neurons, recurrent feedback, and 2-of-3 triple-window majority voting.
911	Simon Says memory game	Uri Shaked	Repeat the sequence of colors and sounds to win the game
928	Tiny SCAN chain tester	Pablo Mendoza Ponce	Test module to lear about scan chains
930	DMA	Terry Lu	Direct Memory Access module
932	VAK FSM	Sam Weber	The FSM for the VAK lab at Northwestern
934	Streaming Sobel Edge Detection Accelerator	Zihang Cheng	Streaming Sobel edge detection ASIC using line-buffer based 3x3 convolution for grayscale image processing
936	8-Bit Error Detection Engine	Himadri Ghosh, Aditya Panigrahi, Chiranjeet Bhattacharjee, Debaditya Dasgupta, Subir Kr. Maity	A multiplexed combinational engine providing Hamming(12,8) and CRC-8 data protection for high-reliability 8-bit SoC communication.
938	Translator	Nano CNMN IPN	Translates Morse code and displays plaintext on seven-segment displays
940	CPU 8 bits	Nano CNMN IPN	An 8-bit CPU that performs instructions such as arithmetic and load instructions, and outputs the result of each instruction.
942	IEEE_MMU_Logo	Au Kai Zhe, Lim Zing	Display the logo of Multimedia University (MMU) with VGA
960	IEEE bfloat16_accelerator	Jorge I. Marin	SPI accelerator for continuous bfloat16 operations (SUM/SUB/MPY)
961	movingscreen	llhtimlam	movingscreen
962	IEEE_DSP_FIR	Lim Zing, Au Kai Zhe	Digital Signal Processor using Finite Impulse Response (FIR) Filter
963	harveywilly	Harvey, William	tiny tapeout demo
964	Charlieplex array controller	Tim Edwards	Charlieplex LED array controller with UART programming
965	Checkers	Andy Duong	Checkers display
966	wave_hi	bytex64	I didn't have time to make something good, so I thought I'd send you a wave.
967	Iterative MAC LATCHUP2026	RajuMachupalli	32-bit iterative MAC with 7x8-bit multiplier for AI/ML acceleration (LatchUp 2026)
968	IEEE PWM Generator	Maria Jose Huiza	2-bit PWM generator with configurable duty cycle via reference bits
969	Caleb's Checkers	Caleb Bulboaca	Checkers VGA project with modified layer movements and colours
970	Jitter Metrics & Pulse Analyzer	Gustavo Ismael Chavez Mamani	High-speed Jitter measurement tool with UART interface and hardware gating
971	ttsky-verilog-yk	Yusef Karim	VGA logo
972	Reaction game on Simon Says board	Mikkel Heise Kofoed	Testing your reaction time
973	Latch Up Tiny Tapeout	lfearn	VGA display
974	IEEE Open-Silicon 2026: Load Priority Controller	Abiola Enoch, Omotosho Enoch, Esabu Blessing	An IEEE Division 1 Open Silicon Tapeout Initiative - Smart hardware FSM with staged load activation, noise filtering, and load shedding for power-constrained systems. No firmware required.
975	7x8 Charlieplex Array Controller	Wadood Wasay	Custom controller for Adafruit Charlieplex LED array board
992	Simon Memory Game Chip	Isabella López & Marlon Carriel	A simple Simon Says memory game implemented in Verilog using a RAM and FSM.
994	(IEEE) USP OpenSilicio Didactic Testchip	USP OpenSilicio Group (IEEE)	Didactic chip for teaching CMOS design at USP. Five modules selected by a 3-bit main MUX: logic gate library, ring oscillator with 24-bit configurable divider, phase-frequency detector (PFD), D/T flip-flop study, and 4-bit binary counter.
996	Bernoulli Stochastic Multiplier + LIF Neuron	Evan Smith	Multiplies two 4-bit values via Bernoulli streams with conventional multiplier comparison; LIF neuron on same tile
998	tinyWorkshop	advun	Compresses trace data in one clock cycle through simple and space efficient compression algorithm
1000	Trial IB	Ibo Bob	test
1002	IEEE 8-bit AXI4-Stream FWFT FIFO	Benedictus Kenneth Setiadi	An 8-bit depth-16 AXI4-Stream FIFO with First-Word Fall-Through (FWFT) using register file.
1004	QuadPulse — 4-Channel Servo/Motor PWM ASIC	Sarvesh S	A dedicated 4-channel PWM generator ASIC for servo and DC motor control in robotic systems. Eliminates software timing jitter by implementing PWM generation entirely in silicon. Supports 50 Hz servo control through 20 kHz motor drive. SPI interface allows runtime duty cycle updates from any microcontroller. Hardware emergency stop instantly silences all channels. Designed for autonomous robotic swarm applications where deterministic multi-channel motor control is critical.
1006	V-SPACE Demo: Command & Control Chronograph	Advaittej	Interactive 1Hz stopwatch with hardware debouncing, lap memory, alarm target, and 9600-baud UART RX/TX telemetry.