750 TRI-1 Gamma — MAX-TRUE NEUROMORPHIC FLAGSHIP 32-tile 8-column
750 : TRI-1 Gamma — MAX-TRUE NEUROMORPHIC FLAGSHIP 32-tile 8-column
- Author: Dmitrii Vasilev
- Description: MAX-TRUE NEUROMORPHIC FLAGSHIP SKU of the TRI-1 Triad (TTSKY26b). 32 tiles = 8x4 TT footprint. Architecture: 8 cortical columns (cortical_column.v — LIF leaky-integrate-and-fire dynamics with 8-bit membrane potential, BitNet b1.58 ternary MLP hidden layer, GF16 dot4 input projection, sparse PE accumulator; ~500 cells/column = ~4100 total) + 20-PE GF16 mesh (1x trinity_quad_mesh 16 PE + 1x trinity_mesh_2x2 4 PE) + 24 SUPER-CROWN modules (phi_anchor_post, lucas_rom x7, vsa_matmul_8x8, vsa_matmul_16x16, bitnet_encoder, bpb_counter, blake3_anchor, multi_tile_receipt, crc32_receipt, alu9_decoder, ring27_memory, hwrng_lfsr, phi_pll_div, wb_status_reg, wishbone_full, trinity_master_fsm, trinity_mesh_2x2, gf16_dot4, plus 6 PhD-anchored monitors: cassini_post, plrm_counter, bpb_lower_bound_guard, nca_entropy_monitor, strobe_seed_guard, phi_distance_oracle) + D2D holo mesh 4-port N/E/S/W router (d2d_holo_mesh.v — adapted from tt-trinity-holo TTSKY26c lineage; uio[3:0]=TX, uio[7:4]=RX inputs; LAYER-FROZEN gate on w_tx per PhD Theorem 36.1 R18) + full Crown47 ROM (crown47_rom + crown47_rom_8bit) + TRI NET friend/foe handshake (GAMMA anchor 8'h93) + FHRR holo_lut_pe (VSA binding, Glava 32). v1.0.0 enhancements: GF4/GF8/GF12/GF16/GF20/GF24/GF32/GF64/GF128/GF256 formats, quantizers (Int4/Int8/NF4/FP8_E4M3/FP8_E5M2/Posit16), sacred opcodes (0xDF LUT_LOOKUP, 0xE1 SPARSE_SKIP, 0xE3 LUT_NPU, 0xE5 SUBTH_CLK, 0xE6 HOLO_MUX_X4, 0xE7 DFS_GATE, 0xE8 SPARSE_SKIP2, 0xE9 STOCH_ROUND, 0xEA NULL_PE, 0xEB SPEC_EXIT, 0xEC DROWSY_RET), power modules (AVS-48/96, FBB, Purkinje thermal). TOPS/W: 75 baseline, 405 with AVS-96. TG-TRIAD-X canonical anchor 0x47C0 on {uio_out,uo_out} at reset (PhD Theorem 36.1, docs/phd/chapters/flos_70.tex). R-SI-1: zero NEW * operators (legacy gf16_mul grandfathered per TRI_NET_SHUTTLE_TRIAD.md Rule 2 / tt-trinity-gf16#4). Anchor: phi^2 + phi^-2 = 3. DOI: 10.5281/zenodo.19227877. tt-trinity-holo D2D lineage (TTSKY26c, 1x2, r_marker_rom.v). S-13 dual-lib: sky130_fd_sc_hd primary + sky130_fd_sc_hdll for low-activity blocks. See docs/L-DPC22-K-DUAL-LIB.md.
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- Clock: 50000000 Hz
Trinity Gamma — 8x4 Neuromorphic Flagship
Largest sibling of the Trinity TTSKY26b triad. 32 tiles (8x4) neuromorphic accelerator with 8 cortical columns, 20-PE GF16 mesh, 24 SUPER-CROWN modules, 6 PhD-anchored monitors, and a 4-port die-to-die holographic mesh router.
How it works
The design integrates several blocks around the canonical Trinity anchor:
- 8 cortical columns with LIF dynamics, BitNet b1.58 ternary MLP, GF16 dot4 projection, and sparse PE accumulator (~500 cells per column)
- GF16 mesh: 1 trinity_quad_mesh (16 PE) plus 1 trinity_mesh_2x2 (4 PE)
- 24 SUPER-CROWN modules: phi_anchor_post, 7 Lucas ROMs, vsa_matmul 8x8 and 16x16, BitNet encoder, BPB counter, Blake3 anchor, multi-tile receipt, CRC32 receipt, ALU9 decoder, ring27 memory, HW RNG LFSR, phi PLL divider, Wishbone status, full Wishbone, trinity master FSM, trinity_mesh_2x2, gf16_dot4
- 6 PhD-anchored monitors: cassini_post, plrm_counter, bpb_lower_bound_guard, nca_entropy_monitor, strobe_seed_guard, phi_distance_oracle
- 4-port die-to-die holographic mesh router (N/E/S/W) for multi-chip spike propagation
- Crown47 ROM encoding 47 fundamental constants in 24-bit pseudo-float
GF16 format: 1 sign + 6 exponent (bias=31) + 9 mantissa. All mantissa multiplies use shift-and-add (zero new standalone star operators in synthesisable RTL).
On reset the chip drives the canonical Trinity anchor 0x47C0 onto the output pins. This is the same constant emitted by the Phi (1x1) and Euler (8x2) siblings.
How to test
After reset (ui_in = 0x00):
- uo_out = 0xC0 (result low byte)
- uio_out = 0x47 (result high byte)
Combined: 0x47C0 = GF16(30.0) = dot4(1, 2, 3, 4) (1, 2, 3, 4).
To select packet path mode, drive ui_in[0] high. To probe the Lucas ROM, drive lucas_idx[2:0] on ui_in[3:1].
External hardware
No external hardware required. The die-to-die mesh pins (uio_out[3:0] TX and uio_in[7:4] RX) are directly observable; in a single-die test they can be left unconnected.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | load_mode (0=canonical 0x47C0 default, 1=packet path + status_byte) | result[0] (canonical 0x47C0 default; mesh result_lo[0] after FSM) | D2D n_tx — North TX (output): spike_count[3] activity bit |
| 1 | lucas_idx[0] | result[1] | D2D e_tx — East TX (output): spike_count[0] activity bit |
| 2 | lucas_idx[1] | result[2] | D2D s_tx — South TX (output): GF16 route tag bit |
| 3 | lucas_idx[2] | result[3] | D2D w_tx — West TX SYNC strobe (output, LAYER-FROZEN gated per PhD Thm 36.1 R18) |
| 4 | tri_status_msb (ui[4:2]=3b111 → token balance on uo/uio_out) | result[4] | D2D n_rx — North RX (input from peer die) |
| 5 | unused (ui[4:2] tri_status decoded, ui[7:5] unused) | result[5] | D2D e_rx — East RX (input from peer die) |
| 6 | crown_addr[6:0] MSB (with ui[5:0]) | result[6] | D2D s_rx — South RX (input from peer die) |
| 7 | unused | result[7] | D2D w_rx (input from peer die) / crown_mode enable when high + load_mode=0 |