199 IEEE Tiny 8bit CPU
199 : IEEE Tiny 8bit CPU
- Author: Korichi Aymene, Bouyahiaoui Hadjer, Boubraa Nadjib
- Description: A tiny compact 8-bit 4 general register CPU with 16 instructions
- GitHub repository
- Open in 3D viewer
- Clock: 10000000 Hz
How it works
This project is a compact 8-bit teaching CPU with a 4-register file.
It is configured for 2 Tiny Tapeout tiles (1x2).
Architecture:
- 2-phase control FSM (fetch and execute)
- 4 general 8-bit registers (
r0tor3), withr0hardwired to zero - 5-bit program counter (PC)
- 8-bit instruction register (IR)
- 24x8 data RAM
- 8-bit ALU for add, sub, logic, shift, and simple register moves
Instruction format uses ui_in[7:4] as opcode and ui_in[3:0] as operand.
For register-format instructions, operand[3:2] is rd and operand[1:0] is rs.
Supported opcodes:
0x0: LDI (rd = immediate[1:0])0x1: ADD (rd = rd + rs)0x2: SUB (rd = rd - rs)0x3: STO (RAM[rs] = rd)0x4: LDM (rd = RAM[rs])0x5: JMPZ (if zero flag is set,PC = PC + sign_extend(operand[3:0]))0x6: AND (rd = rd & rs)0x7: OR (rd = rd | rs)0x8: XOR (rd = rd ^ rs)0x9: SHL (rd = rd << rs[2:0])0xA: SHR (rd = rd >> rs[2:0])0xB: JMPNZ (if zero flag is clear,PC = PC + sign_extend(operand[3:0]))0xC: MOV (rd = rs)0xD: INC (rd = rd + 1)0xE: DEC (rd = rd - 1)0xF: NOP
Outputs:
uo_out[7:0]= current destination register (rd) value from the register fileuio_out[6]= latched carry flag from the last register writeuio_out[5]= zero flaguio_out[4:0]= PC debug (PC[4:0])uio_out[7]= fetch phase flag
All logic is synchronous to clk and gated by ena. Reset (rst_n) initializes registers, PC, IR, control state, and RAM.
Instruction bytes are supplied externally on ui_in; there is no on-chip program ROM in the current build.
How to test
Run top-level CPU tests:
cd test
pip install -r requirements.txt
make -B
Run per-module unit tests:
cd test/unit
make -B DUT=alu
make -B DUT=control_fsm
make -B DUT=registers
make -B DUT=memory
make -B DUT=control_unit
make -B DUT=datapath
For waveform inspection, open tb.fst with GTKWave or Surfer.
External hardware
You may need to add an external memory to store instructions and feed it to cpu through ui_in, and use 5bit PC as an address.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | instr_bit0 | rd_bit0 | pc_bit0_debug |
| 1 | instr_bit1 | rd_bit1 | pc_bit1_debug |
| 2 | instr_bit2 | rd_bit2 | pc_bit2_debug |
| 3 | instr_bit3 | rd_bit3 | pc_bit3_debug |
| 4 | instr_bit4 | rd_bit4 | pc_bit4_debug |
| 5 | instr_bit5 | rd_bit5 | zero_flag_debug |
| 6 | instr_bit6 | rd_bit6 | carry_flag_debug |
| 7 | instr_bit7 | rd_bit7 | fetch_phase_debug |