
This project implements an 8-bit, depth-16 AXI4-Stream FIFO with First-Word Fall-Through (FWFT) characteristics.
Instead of using traditional Block RAM (BRAM) which introduces a 1-clock cycle read latency, this design utilizes a Register File (D-Flip-Flops) for its storage element. This architectural choice allows for asynchronous, combinational reads. As a result, when data is written to the FIFO, it immediately "falls through" to the output bus on the same clock cycle without requiring a read strobe, providing true 0-cycle latency FWFT behavior.
The FIFO manages AXI4-Stream handshaking using tvalid and tready signals on both the master and slave interfaces, and provides internal 5-bit pointers to evaluate full and empty conditions.
The design can be tested by providing a 50 MHz clock to the clk pin and managing the AXI-Stream control signals.
Write Operation (Producer):
ui_in[7:0] (s_axis_tdata).uio_in[0] (s_axis_tvalid) to HIGH.uio_out[1] (s_axis_tready). If HIGH, the data is successfully written on the rising clock edge.Read Operation (Consumer):
uo_out[7:0] (m_axis_tdata).uio_out[3] (m_axis_tvalid) being HIGH.uio_in[2] (m_axis_tready) to HIGH to consume the data and advance the read pointer.Debug flags are available on uio_out[4] (FIFO Full) and uio_out[5] (FIFO Empty).
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | s_axis_tdata[0] | m_axis_tdata[0] | s_axis_tvalid (Input from Producer) |
| 1 | s_axis_tdata[1] | m_axis_tdata[1] | s_axis_tready (Output to Producer) |
| 2 | s_axis_tdata[2] | m_axis_tdata[2] | m_axis_tready (Input from Consumer) |
| 3 | s_axis_tdata[3] | m_axis_tdata[3] | m_axis_tvalid (Output to Consumer) |
| 4 | s_axis_tdata[4] | m_axis_tdata[4] | fifo_full_flag (Output - Debug) |
| 5 | s_axis_tdata[5] | m_axis_tdata[5] | fifo_empty_flag (Output - Debug) |
| 6 | s_axis_tdata[6] | m_axis_tdata[6] | NC (Not Connected) |
| 7 | s_axis_tdata[7] | m_axis_tdata[7] | NC (Not Connected) |