172 1-bit Perceptron - Hardware Neuron
172 : 1-bit Perceptron - Hardware Neuron
- Author: Jacob Kirera
- Description: A single artificial neuron (perceptron) implemented in pure combinational logic. Four binary inputs are each multiplied by a 2-bit weight, summed in an adder tree, and compared to a configurable threshold. The neuron fires (output = 1) when the weighted sum meets or exceeds the threshold.This is the fundamental building block of every neural network — on real silicon. Weights and threshold are set live via input pins, making it fully reconfigurable without re-synthesis.
- GitHub repository
- Open in 3D viewer
- Clock: 0 Hz
How it works
This project implements a 1-bit artificial neuron (perceptron) in pure combinational logic on silicon.
The Perceptron Algorithm
The design computes the fundamental neuron equation:
$y = (x_0 \cdot w_0 + x_1 \cdot w_1 + x_2 \cdot w_2 + x_3 \cdot w_3) \geq \text{threshold}$
where:
- x₀–x₃ are 4 binary inputs (0 or 1)
- w₀–w₃ are 4 programmable integer weights (0–3, each 2 bits)
- threshold is a programmable firing threshold (range 1–4, set via 2-bit config)
- y is the binary neuron output (1 = fires, 0 = silent)
Pin Mapping
Dedicated Inputs (ui_in[7:0])
ui_in[3:0]: Binary inputs x₀, x₁, x₂, x₃ui_in[5:4]: Weight w₀ (2 bits, value 0–3)ui_in[7:6]: Weight w₁ (2 bits, value 0–3)
Bidirectional IOs (uio_in[7:0])
uio_in[1:0]: Weight w₂ (2 bits, value 0–3)uio_in[3:2]: Weight w₃ (2 bits, value 0–3)uio_in[5:4]: Threshold config (2 bits; actual threshold = config + 1, so 1–4)uio_in[7:6]: Unused
Dedicated Outputs (uo_out[7:0])
uo_out[0]: Neuron output y (1 if fires, 0 if silent)uo_out[4:1]: Weighted sum (4-bit debug output, range 0–12)uo_out[7:5]: Unused (tied low)
Hardware Implementation
The design uses a three-stage datapath:
- Weighted Multiply: Each input x is multiplied by its weight w using an AND gate (since inputs are binary, multiplication is gating).
- Sum Tree: Three levels of addition fold four 2-bit terms into a single 4-bit sum.
- Threshold Compare: The sum is compared against the threshold to produce the final 1-bit neuron output.
This is purely combinational logic (no clock, no state), so the output is valid the instant all inputs are set.
How to test
The design includes a comprehensive cocotb testbench covering five key neuron behaviors.
Running the Tests
cd test/
make
This builds the RTL simulation using Icarus Verilog and runs all testbench modules via cocotb.
Test Cases
-
test_zero_inputs: Verifies the neuron remains silent when all inputs are 0, regardless of weights or threshold.
-
test_or_gate: Configures the neuron as an OR gate (w₀=w₁=w₂=w₃=1, threshold=1). The neuron should fire if any input is 1.
-
test_and_gate: Configures the neuron as an AND gate (w₀=w₁=w₂=w₃=1, threshold=4). The neuron fires only when all four inputs are 1.
-
test_weighted_sum: Tests the arithmetic of the weighted sum stage with hand-calculated cases:
- [1,0,0,0] × [3,2,1,0] → sum = 3
- [1,1,0,0] × [2,2,2,2] → sum = 4
- [1,1,1,1] × [1,2,3,3] → sum = 9
- [0,1,0,1] × [3,3,3,3] → sum = 6
- [1,0,1,0] × [2,0,2,0] → sum = 4
-
test_threshold_sweep: Verifies the firing boundary by sweeping the threshold:
- With sum=4, the neuron fires for all threshold configs (1, 2, 3, 4).
- With sum=2, the neuron fires for thresh configs 0–1 (actual thresholds 1–2) but not 2–3 (thresholds 3–4).
Viewing Waveforms
The testbench generates a waveform file (tb.fst). To visualize with GTKWave:
gtkwave tb.fst tb.gtkw
External hardware
None. This is a pure digital design with no external dependencies.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | x0 — binary input 0 | y — neuron output (1=fires, 0=silent) | w2[0] — weight 2, bit 0 |
| 1 | x1 — binary input 1 | sum[0] — weighted sum bit 0 (debug) | w2[1] — weight 2, bit 1 |
| 2 | x2 — binary input 2 | sum[1] — weighted sum bit 1 (debug) | w3[0] — weight 3, bit 0 |
| 3 | x3 — binary input 3 | sum[2] — weighted sum bit 2 (debug) | w3[1] — weight 3, bit 1 |
| 4 | w0[0] — weight 0, bit 0 | sum[3] — weighted sum bit 3 (debug) | thresh[0] — threshold bit 0 |
| 5 | w0[1] — weight 0, bit 1 | unused | thresh[1] — threshold bit 1 |
| 6 | w1[0] — weight 1, bit 0 | unused | unused |
| 7 | w1[1] — weight 1, bit 1 | unused | unused |