
This project implements a structural 4-bit Ripple Carry Adder (RCA). It computes the arithmetic sum of two 4-bit unsigned binary numbers ($A$ and $B$) and generates a 5-bit result ($S$).
The hardware architecture uses a modular, multi-stage structure:
sumadormedio) processes $A[0]$ and $B[0]$ to produce the first sum bit $S[0]$ and an initial carry-out $C[0]$.sumadorcompleto) sequentially cascade the carry-out from the previous stage ($C_{in}$) with the respective input bits ($A[i]$ and $B[i]$) to compute $S[i]$ and the next $C_{out}$.Since this design does not include sequential elements (registers or flip-flops), it operates entirely as a combinational block. The global clock (clk), reset (rst_n), and enable (ena) inputs are properly tied off internally to avoid linting warnings during the OpenLane/Yosys synthesis flow.
To test the operation of the 4-bit adder on the TinyTapeout demoboard:
ui_in[3:0] to set the 4-bit binary value for operand A.
ui_in[7:4] to set the 4-bit binary value for operand B.uo_out[4:0].uo_out[0] corresponds to the LSB ($S[0]$), and uo_out[4] corresponds to the final carry-out / MSB ($S[4]$).uo_out[7:5] will stay at a logic low level (0).For example, if you set $A = 0101$ (5 in decimal) on ui_in[3:0] and $B = 0111$ (7 in decimal) on ui_in[7:4], the output pins uo_out[4:0] will display 01100 (12 in decimal).
No specialized external hardware are strictly required.
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | A[0] | S[0] | |
| 1 | A[1] | S[1] | |
| 2 | A[2] | S[2] | |
| 3 | A[3] | S[3] | |
| 4 | B[0] | S[4] (Cout) | |
| 5 | B[1] | ||
| 6 | B[2] | ||
| 7 | B[3] |