77 Sigma-Delta Bitstream ADC (8-bit)
77 : Sigma-Delta Bitstream ADC (8-bit)
- Author: William Anthony
- Description: Enable-controlled 1-bit sigma-delta decimator ADC with gain and offset trim
- GitHub repository
- Open in 3D viewer
- Clock: 13560000 Hz
How it works
This design is a digital ADC chain for 1-bit sigma-delta bitstreams.
- The incoming bitstream (
ui[1]) is sampled by the Tiny Tapeout clock. - A 256-cycle decimator counts ones to produce a raw 8-bit code.
- Gain trim (
uio[3:0]) and signed offset trim (ui[7:4]) are applied. - The calibrated conversion result is output on
uo[7:0].
Status bits are exported on uio[7:4] as {saturated, activity, busy, valid}.
How to test
- Go to the
testfolder. - Run RTL simulation:
make -B
- The cocotb test checks conversion and status behavior:
- No
validpulse while disabled. - Correct decimation code for known bit densities.
- Correct gain/offset calibration behavior.
- Saturation flag assertion on clipped samples.
- Activity flag response for dynamic vs static input windows.
- No
You can inspect waveforms using GTKWave:
gtkwave tb.fst tb.gtkw
External hardware
No external hardware is required for RTL verification.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | ADC enable | ADC output bit 0 | Gain trim bit 0 (input) |
| 1 | 1-bit sigma-delta bitstream input | ADC output bit 1 | Gain trim bit 1 (input) |
| 2 | Reserved | ADC output bit 2 | Gain trim bit 2 (input) |
| 3 | Reserved | ADC output bit 3 | Gain trim bit 3 (input) |
| 4 | Offset trim bit 0 (signed) | ADC output bit 4 | Valid pulse (output) |
| 5 | Offset trim bit 1 (signed) | ADC output bit 5 | Busy status (output) |
| 6 | Offset trim bit 2 (signed) | ADC output bit 6 | Activity status (output) |
| 7 | Offset trim bit 3 (signed) | ADC output bit 7 | Saturation status (output) |