932 8-Bit Error Detection Engine
932 : 8-Bit Error Detection Engine
- Author: Himadri Ghosh, Aditya Panigrahi, Chiranjeet Bhattacharjee, Debaditya Dasgupta, Subir Kr. Maity
- Description: A multiplexed combinational engine providing Hamming(12,8) and CRC-8 data protection for high-reliability 8-bit SoC communication.
- GitHub repository
- Open in 3D viewer
- Clock: 0 Hz
How it works
This project is a high-reliability Combinational Error Detection Engine that combines two layers of data protection: Hamming(12,8) encoding and a CRC-8 checksum. Unlike serial designs, this engine provides zero-latency encoding by using pure XOR trees.
Encoding Layer 1 (Hamming): The 8-bit data from ui_in is instantly processed through a Hamming(12,8) XOR tree to generate 4 parity bits, creating a 12-bit protected codeword.
Encoding Layer 2 (CRC): The 12-bit Hamming word is simultaneously fed into a secondary XOR tree to calculate an 8-bit CRC-8 checksum (Polynomial 0x07).
Multiplexed Output: Because the final protected frame is 20 bits wide (12 bits Hamming + 8 bits CRC), it exceeds the 8-bit output limit. The design uses a 4-to-1 multiplexer controlled by uio_in[1:0] to allow a receiver to read the full 20-bit codeword in three 8-bit chunks.
How to test
Testing is performed by setting the input data and toggling the selection bits to read the protected segments:
Input Data: Set your 8-bit test pattern on ui_in[7:0].
Read Segment 0 (MSB): Set uio_in[1:0] to 00. uo_out[3:0] will show the 4 most significant bits of the Hamming codeword (padded with leading zeros).
Read Segment 1 (Mid): Set uio_in[1:0] to 01. uo_out[7:0] will show the 8 least significant bits of the Hamming codeword.
Read Segment 2 (CRC): Set uio_in[1:0] to 10. uo_out[7:0] will show the 8-bit CRC checksum.
Bypass Check: Set uio_in[1:0] to 11. uo_out[7:0] should exactly match your ui_in value.
External hardware
Microcontroller / FPGA: An external controller is needed to cycle through the select states (00, 01, 10) and capture the output to reconstruct the 20-bit protected frame.
Logic Analyzer: Highly recommended to verify that the transitions between select states result in the correct bit segments.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | data_in[0] | out[0] | select[0] |
| 1 | data_in[1] | out[1] | select[1] |
| 2 | data_in[2] | out[2] | unused |
| 3 | data_in[3] | out[3] | unused |
| 4 | data_in[4] | out[4] | unused |
| 5 | data_in[5] | out[5] | unused |
| 6 | data_in[6] | out[6] | unused |
| 7 | data_in[7] | out[7] | unused |