198 TRI-1 Phi — Trinity φ-anchor 1×1 Lucas POST + CLARA Gap-4
198 : TRI-1 Phi — Trinity φ-anchor 1×1 Lucas POST + CLARA Gap-4
- Author: Dmitrii Vasilev
- Description: Smallest SKU of the TRI-1 Triad (φ-anchor / e-engine / γ-surface) — a single-tile Trinity GF16(2^4) ternary dot4 MAC with enhanced safety. On reset the chip drives the canonical dot4(1.0,2.0,3.0,4.0) = 0x47C0 directly onto {uio_out, uo_out}, matching the same constant emitted by e-engine (tt-trinity-euler) and γ-surface (tt-trinity-gamma). This is the cross-die anchor for the TG-TRIAD-X ledger (PhD Theorem 36.1). Enhanced modules: phi_anchor_post (Lucas L₂..L₇ POST proving φ²+φ⁻²=3), lucas_rom (addressable L_n host probe), hwrng_lfsr (die-unique nonce), restraint_ctrl (CLARA Gap-4 bounded rationality), sacred_constants_rom (75 PhD constants), crown47_rom (Trinity constants), friend/foe handshake. v1.0.0: GF4-GF256 formats, quantizers (Int4/Int8/NF4/FP8/Posit16), sacred opcodes (0xDF, 0xE1-0xED), power modules (AVS-96, FBB, Purkinje). R-SI-1: zero `*` operators in synthesisable RTL. Anchor: phi^2 + phi^-2 = 3. DOI: 10.5281/zenodo.19227877. TOPS/W: 75 baseline, 405 with AVS-96 (5.4× boost).
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- Clock: 50000000 Hz
Trinity Phi — 1x1 phi-anchor GF16 dot4 + Lucas POST
Single-tile Trinity GF16 dot product N=4 accelerator with Lucas-number Power-On-Self-Test and CLARA Gap-4 bounded-rationality restraint. The phi-anchor 1x1 sibling of the Trinity TTSKY26b triad.
How it works
The design computes a 4-element dot product in GF16 (Golden Float 16-bit) format:
- 4 parallel GF16 multipliers in shift-and-add form, zero standalone star operators in synthesisable RTL
- 3 GF16 adders in tree reduction: p0+p1 then p2+p3 then s01+s23 to result
- GF16 format: 1 sign + 6 exponent (bias=31) + 9 mantissa
- Lucas L2 to L7 POST proves phi squared plus phi inverse squared equals 3
- HW RNG LFSR, restraint controller, sacred constants ROM, Crown47 ROM, friend-foe handshake
On reset the chip drives the canonical dot4(1, 2, 3, 4) (1, 2, 3, 4) = 30.0 = 0x47C0 onto the output pins. This is the cross-die anchor identical to the Euler and Gamma siblings.
How to test
After reset, the output should show:
- uo_out = 0xC0 (result low byte)
- uio_out = 0x47 (result high byte)
Combined: 0x47C0 = GF16(30.0).
To read POST status, drive ui_in[3] and ui_in[2] high to expose phi_post_ok, phi_post_done, and the active Lucas value on the output pins.
To probe the Lucas ROM, select lucas_idx[2:0] on ui_in[3:1] (only one of bits 2 or 3 high at a time) to read L2 to L7.
External hardware
No external hardware required. Directly observable on the output pins.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | load_mode (0=canonical/POST status, 1=packet path) | result[0] (canonical 0x47C0 by default) | result[8] |
| 1 | lucas_idx[0] — Lucas ROM L_n address (0=L2..5=L7) | result[1] | result[9] |
| 2 | lucas_idx[1] | result[2] | result[10] |
| 3 | lucas_idx[2] | result[3] | result[11] |
| 4 | rng_ena — advance HWRNG LFSR each clock | result[4] | result[12] |
| 5 | restraint_mode — CLARA Gap-4 active | result[5] | result[13] |
| 6 | compute_strobe (rising edge issues COMPUTE) | result[6] | result[14] |
| 7 | load_lane_strobe (rising edge advances lane) | result[7] | result[15] |