
QuadPulse generates 4 independent, jitter-free PWM signals for servo and DC motor control. It uses a 10 MHz system clock divided into a configurable PWM period, with a phase accumulator ramp giving 8-bit (256-step) duty cycle resolution at all frequencies.
A 3-wire SPI interface accepts 16-bit frames (2-bit channel address + 8-bit duty value) to load duty cycles at runtime without CPU involvement. A hardware emergency stop pin (ui_in[0]) instantly forces all outputs to zero via combinational logic — no latency.
All SPI inputs pass through 2-stage flip-flop synchronisers to prevent metastability from the asynchronous SPI clock domain. The frequency selector is registered to suppress DIP switch bounce. Four frequency modes are supported: 50 Hz (hobby servos), 1 kHz, 10 kHz, and 20 kHz (silent motor drivers).
Set the frequency with ui_in[2:1]: 00=50 Hz, 01=1 kHz, 10=10 kHz, 11=20 kHz.
Send a 16-bit SPI frame via uio[0] (MOSI), uio[1] (SCLK), uio[2] (CS_N active-low):
Observe PWM outputs on uo_out[3:0]. Connect an LED through a 470 ohm resistor to uo_out[0] to see duty cycle as brightness without an oscilloscope. Set ui_in[0]=1 to trigger emergency stop (all outputs go to 0 immediately, uo_out[4] goes HIGH).
Run the cocotb simulation test suite with cd test && make
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | Emergency Stop — HIGH forces all PWM outputs to 0 | PWM Channel 0 output (Servo 1 / Motor 1) | SPI MOSI — serial data from microcontroller to chip |
| 1 | Freq select bit 0 — 00=50Hz 01=1kHz 10=10kHz 11=20kHz | PWM Channel 1 output (Servo 2 / Motor 2) | SPI SCLK — SPI clock from microcontroller |
| 2 | Freq select bit 1 | PWM Channel 2 output (Servo 3 / Motor 3) | SPI CS_N — chip select, active LOW |
| 3 | PWM Channel 3 output (Servo 4 / Motor 4) | ||
| 4 | Emergency Stop flag — HIGH when emergency stop is active | ||
| 5 | |||
| 6 | |||
| 7 |