207 2x2 Systolic Array TPU
207 : 2x2 Systolic Array TPU
- Author: PFW Tiny Tapeout Team
- Description: A 2x2 systolic-array Tensor Processing Unit that performs signed 8-bit matrix multiplication with 16-bit accumulation, optional fused transpose, and ReLU activation. Pipelined streaming allows overlapped input/output.
- GitHub repository
- Open in 3D viewer
- Clock: 50000000 Hz
How it works
This project implements a small-scale Tensor Processing Unit (TPU) that performs 2x2 matrix multiplications using a systolic array of Multiply-Accumulate (MAC) units. It is designed for the Tiny Tapeout ASIC flow.
Architecture
- Processing Element (PE): Each PE executes a multiply-accumulate operation and propagates partial data to its neighbors in the systolic array.
- Systolic Array (2x2): A mesh of 4 PEs wired in systolic fashion. Data flows left-to-right (weights) and top-to-bottom (inputs).
- Unified Memory: An 8-byte register bank storing both weight and input matrices (4 bytes each).
- Control Unit: A finite-state machine (FSM) sequences the load, compute, and output phases.
- MMU Feeder: Schedules data flow between memory, the systolic array, and the output port.
Features
- Signed 8-bit inputs, 16-bit outputs: Handles signed integers (-128 to 127) and accumulates products in 16-bit precision.
- Pipelined streaming: Supports overlapped input of the next matrix pair while outputting results of the current multiplication.
- Fused transpose: Optional on-chip transpose of the second input matrix (enabled via
uio_in[1]). - ReLU activation: Optional ReLU (clamp negatives to 0) on the output (enabled via
uio_in[2]).
Pin Mapping
| Pin | Direction | Signal |
|---|---|---|
ui_in[7:0] |
Input | 8-bit matrix data |
uo_out[7:0] |
Output | 8-bit result data (half of 16-bit element) |
uio_in[0] |
Input | LOAD_EN: enable loading elements into memory |
uio_in[1] |
Input | TRANSPOSE: enable fused transpose of second operand |
uio_in[2] |
Input | ACTIVATION: enable ReLU activation on output |
uio_out[5] |
Output | STATE0: FSM state bit 0 |
uio_out[6] |
Output | STATE1: FSM state bit 1 |
uio_out[7] |
Output | DONE: high when results are ready |
How to test
- Reset: Assert
rst_nlow for several clock cycles, then release. - Load matrices: Set
uio_in[0](LOAD_EN) high and send 8 bytes viaui_inone per clock cycle: 4 weight elements followed by 4 input elements (row-major order). - Wait for computation: Deassert LOAD_EN and wait. The
DONEsignal (uio_out[7]) goes high when results are available. - Read results: Each of the 4 output elements is 16 bits, streamed as 2 consecutive 8-bit values on
uo_out(high byte first). 8 clock cycles to read all 4 elements. - Continuous operation: You can begin loading the next matrix pair while reading results (pipelined).
Simulation
cd test
pip install -r requirements.txt
make
This runs cocotb tests via Icarus Verilog covering identity multiply, general multiply, signed values, and ReLU activation.
External hardware
No external hardware required for basic operation. Connect ui_in and uio_in to a microcontroller or FPGA for data input and control. Connect uo_out and uio_out to read results and status.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | DATA[0] matrix element bit 0 | OUT[0] result data bit 0 | LOAD_EN (input) enable matrix element loading |
| 1 | DATA[1] matrix element bit 1 | OUT[1] result data bit 1 | TRANSPOSE (input) fused transpose of second operand |
| 2 | DATA[2] matrix element bit 2 | OUT[2] result data bit 2 | ACTIVATION (input) enable ReLU on output |
| 3 | DATA[3] matrix element bit 3 | OUT[3] result data bit 3 | (unused) |
| 4 | DATA[4] matrix element bit 4 | OUT[4] result data bit 4 | (unused) |
| 5 | DATA[5] matrix element bit 5 | OUT[5] result data bit 5 | STATE0 (output) FSM state bit 0 |
| 6 | DATA[6] matrix element bit 6 | OUT[6] result data bit 6 | STATE1 (output) FSM state bit 1 |
| 7 | DATA[7] matrix element bit 7 | OUT[7] result data bit 7 | DONE (output) high when results are ready |