TinyQV is a small Risc-V SoC, implementing the RV32EC instruction set, with a couple of caveats:
Instructions are read using QSPI from Flash, and a QSPI PSRAM is used for memory. The QSPI clock and data lines are shared between the flash and the RAM, so only one can be accessed simultaneously.
Code can only be executed from flash. Data can be read from flash and RAM, and written to RAM.
The SoC includes a UART and an SPI controller.
| Address range | Device |
|---|---|
| 0x0000000 - 0x0FFFFFF | Flash |
| 0x1000000 - 0x17FFFFF | RAM A |
| 0x1800000 - 0x1FFFFFF | RAM B |
| 0x8000000 - 0x8000007 | GPIO |
| 0x8000010 - 0x800001F | UART |
| 0x8000020 - 0x8000027 | SPI |
| Register | Address | Description |
|---|---|---|
| OUT | 0x8000000 (W) | Control out0-7, if the corresponding bit in SEL is high |
| OUT | 0x8000000 (R) | Reads the current state of out0-7 |
| IN | 0x8000004 (R) | Reads the current state of in0-7 |
| SEL | 0x800000C (R/W) | Enables general purpose output on the corresponding bit on out0-7 |
| Register | Address | Description |
|---|---|---|
| DATA | 0x8000010 (W) | Transmits the byte |
| DATA | 0x8000010 (R) | Reads any received byte |
| STATUS | 0x8000014 (R) | Bit 0 indicates whether the UART TX is busy, bytes should not be written to the data register while this bit is set. Bit 1 indicates whether a received byte is available to be read. |
| Register | Address | Description |
|---|---|---|
| DATA | 0x8000018 (W) | Transmits the byte |
| STATUS | 0x800001C (R) | Bit 0 indicates whether the UART TX is busy, bytes should not be written to the data register while this bit is set. |
| Register | Address | Description |
|---|---|---|
| DATA | 0x8000020 (W) | Transmits the byte in bits 7-0, bit 8 is set if this is the last byte of the transaction, bit 9 controls Data/Command on out3 |
| DATA | 0x8000020 (R) | Reads the last received byte |
| CONFIG | 0x8000024 (W) | The low 2 bits set the clock divisor for the SPI clock to 2*(value + 1), bit 2 adds half a cycle to the read latency when set |
| STATUS | 0x8000024 (R) | Bit 0 indicates whether the SPI is busy, bytes should not be written or read from the data register while this bit is set. |
Load an image into flash and then select the design.
Reset the design as follows:
Based on the observed latencies from tt3p5 testing, at the target 64MHz clock a read latency of 2 or 3 is likely required. The maximum supported latency is currently 3, but should get up to 5 to have a chance at running at faster clock speeds.
The above should all be handled by some MicroPython scripts for the RP2040 on the TT demo PC.
Build programs using the riscv32-unknown-elf toolchain and the tinyQV-sdk, some examples are here.
The design is intended to be used with this QSPI PMOD on the bidirectional PMOD. This has a 16MB flash and 2 8MB RAMs.
The UART is on the correct pins to be used with the hardware UART on the RP2040 on the demo board.
The SPI controller is intended to make it easy to drive an ST7789 LCD display (more details to be added).
It may be useful to have buttons to use on the GPIO inputs.
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | Interrupt 0 | UART TX | Flash CS |
| 1 | Interrupt 1 | UART RTS | SD0 |
| 2 | SPI MISO | SPI DC | SD1 |
| 3 | GP in3 | SPI MOSI | SCK |
| 4 | GP in4 | SPI CS | SD2 |
| 5 | GP in5 | SPI SCK | SD3 |
| 6 | GP in6 | Debug UART TX | RAM A CS |
| 7 | UART RX | Debug signal | RAM B CS |