This is an attempt to build a DAC with multiple digital modulation schemes on the output. It was originally intended to use the analog pins to output the analog waveform as well, but I ran out of time.
The device will output four types of digital modulation to represent the analog input:
uo[0]uo[2]uo[3]uo[4]The PDM signal is based on tracking an error accumulator, and has the fastest response to changing input. The PWM signal has a frequency that is 1/256th of the input clock frequency (~200kHz at 50MHz input).
The two PFM modes are less useful for actual modulation, but they can effectively do a frequency sweep of the filter on the output.
After connecting the external RC filter, you need to set the clock rate and program the DAC.
The modulation output rate can be divided down from the main clock input by up to 15. The uio[0:3] pins set the clock divisor.
There are two ways to program the DAC, and they can be selected between using the uio[7] pin.
uio[7] = 0: Parallel data input
ui[0:7]uio[4]uio[7] = 1: SPI data input
uio[5] -> SCLKuio[6] -> SDIuio[4] -> CS_LThe modulation outputs are all digital pulses of some sort. In order to get meaningful analog levels, you’ll need to add an RC filter on the output pin that you are using. The cuttoff will depend on what your chosen frequency is and the type of modulation.
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | DAC Parallel Input, bit 0 | PDM Waveform Output | CLK_DIV[0] |
| 1 | DAC Parallel Input, bit 1 | CLK_DIV[1] | |
| 2 | DAC Parallel Input, bit 2 | PFM Output, Single cycle pulse | CLK_DIV[2] |
| 3 | DAC Parallel Input, bit 3 | PFM Output, 50% duty cycle | CLK_DIV[3] |
| 4 | DAC Parallel Input, bit 4 | PWM Waveformn Output | SPI CS_L / Parallel Latch |
| 5 | DAC Parallel Input, bit 5 | SPI SCLK | |
| 6 | DAC Parallel Input, bit 6 | SPI SDI | |
| 7 | DAC Parallel Input, bit 7 | Parallel/SPI Select (0 => Parallel, 1 => SPI) |