16 bad apple

16 : bad apple

Design renderSelect Project123456789ONSW2

How it works

Converts an RTTL ringtone into verilog and plays it back using differential PWM modulation.

How to test

Provide 12kHz clock on io_in[0], briefly hit reset io_in[1] (L->H->L) and io_out[1:0] will play a differential sound wave over piezo speaker (Bad Apple)

External hardware

Piezo speaker connected across io_out[1:0]

IO

#InputOutput
0clockpiezo_speaker_p
1resetpiezo_speaker_n
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