556-15 Subtile factory test :: Quicker, easier and cheaper to make your own chip!

556-15 : Subtile factory test

The subtile factory test module is a simple module that can be used to test all the I/O available to a subtile on an ASIC.

Note: the bidirectional pins are unavailable to subtiles.

It has three modes of operation:

Mirroring the input pins to the output pins (when rst_n is low and clk is high).
Mirroring and inverting the input pins to the output pins (when rst_n is low and clk is low).
Outputting all zeros to the output pins (when rst_n is high, clk doesn't matter).

The following table summarizes the modes:

`rst_n`	`clk`	Mode	uo_out value
0	1	Input mirror	ui_in
0	0	Inverted input mirror	uio_in
1	X	All zeros	`8'b0`

This is implemented in Verilog as:

assign uo_out  = rst_n ? (clk ? ui_in : ~ui_in) : 8'b0;

Set rst_n low and clk high and observe that the input pins (ui_in) are output on the output pins (uo_out).
Set rst_n low and clk low and observe that the input pins (ui_in) are inverted and output on the output pins (uo_out).
Set rst_n high (and clk to anything) and observe that the output pins (uo_out) are all driven low.

#	Input	Output
0	IN0	OUT0
1	IN1	OUT1
2	IN2	OUT2
3	IN3	OUT3
4	IN4	OUT4
5	IN5	OUT5
6	IN6	OUT6
7	IN7	OUT7

Input

Output

Bidirectional

IN0

OUT0

IN1

OUT1

IN2

OUT2

IN3

OUT3

IN4

OUT4

IN5

OUT5

IN6

OUT6

IN7

OUT7

Chip location

556-15 Subtile factory test