
This is a simple VCO experiment using a current-starved ring oscillator. It consists of 5 current-starved inverter stages in a ring, followed by a buffer pair. This is output via ua[1] and also fed to a digital test block where it is divided using a 5-bit synchronous counter and presented on uio_out[5:1], beside a buffered (but non-divided) copy of the VCO output on uio_out[0] (aka osc_out).
For a given input voltage (vin, i.e. ua[0]) in the range 0.55V to 3.3V, the oscillator output (vco_out, i.e. ua[1]) is expected to be a square wave roughly in the range of 2MHz to 400MHz.
vin held at 0V and rst_n high. No TT clk is required. Expect to see no oscillation on vco_out or uio_out[5:1].vin to 0.55V, and you might see vco_out oscillating at about 2MHz, 3.3Vpp, about 50% duty cycle.vin slowly and if vco_out wasn't already oscillating then you should see it start at least by the time vin reaches 0.65V (if not sooner), and as you raise vin further the frequency at vco_out should rapidly increase.uio_out[0], and then halving of the frequency up through each of uio_out[1] to uio_out[5].vin.vco_out.| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | dac_d0 | R1 | avo[0] |
| 1 | dac_d1 | G1 | avo[1] |
| 2 | dac_d2 | B1 | avo[4] |
| 3 | dac_load | VSync | avo[5] |
| 4 | dac_shift | R0 | dvo[0] |
| 5 | vco_disable | G0 | dvo[1] |
| 6 | test_mode | B0 | dvo[4] |
| 7 | vga_mode | HSync | dvo[5] |
ua | PCB Pin | Internal index | Description |
|---|---|---|---|
| 0 | B6 | 12 | ana_vco_vin |
| 1 | B7 | 13 | ana_vco_out |
| 2 | B8 | 14 | dac_vco_vin |
| 3 | B9 | 15 | dac_vco_out |