580 Configurable PWM Generator
580 : Configurable PWM Generator
- Author: Shivaranjani GR, Ganesh Ragava, Sidharth Kamalakkannan
- Description: A PWM generator featuring run-time variable period, duty cycle, and output polarity controls with built-in safety clamps.
- GitHub repository
- Open in 3D viewer
- Clock: 50000000 Hz
Configurable PWM Generator
How it works
This project is a run-time configurable Pulse Width Modulation (PWM) generator featuring dynamic controls for the period, duty cycle, and output signal polarity.
The architecture consists of three core blocks:
- Input Safety Constraints: The hardware automatically enforces design rules. It ensures the operating period never falls below a safe minimum threshold of 3 clock cycles to protect physical chip output pad bandwidth. Additionally, it clamps the duty cycle ceiling so that it can never exceed the designated period, avoiding mathematical overflow errors.
- Up-Counter Engine: When the system is enabled, an internal tracking counter increments on every clock cycle. Rather than counting to a fixed maximum, it monitors the safe period input value. As soon as the counter reaches the boundary threshold, it smoothly resets to zero and loops.
- Output Generation & Polarity Control: The logic continually compares the tracking counter against the active duty cycle input to determine the raw output state. An inversion toggle layer is included to completely flip the resulting signal polarity if requested. The chip concurrently outputs both the primary PWM signal and its inverted, complementary twin. Disabling the module immediately forces both output tracks to zero.
How to test
To test the design, ensure the clock and active-low reset lines are operating correctly.
- Enable the Module: Drive the
enablepin high (ui_in[0]). - Set the Frequency (Period): Apply a target boundary value to the
raw_periodpins (ui_in[4:1]) to set the total loop cycle time. - Set the Pulse Width (Duty Cycle): Apply a target threshold value to the
raw_dutypins (uio[3:0]).- If this value is
0, the primary output will remain flatly deactivated. - If this value matches or exceeds the period, the primary output will achieve a constant active high state (100% duty cycle).
- If this value is
- Test Polarity: Drive the
invertpin high (ui_in[5]) to observe the primary and complementary outputs completely swap their logical signal states. - Test Safe Disarm: Drop the
enablepin low; both outputs must instantly drive to zero.
External hardware
- Standard Tiny Tapeout Demo Board input DIP switches (to adjust period, duty cycle, and toggles).
- Standard Tiny Tapeout Demo Board output LEDs (to observe the brightness change from the PWM output).
- (Optional) An oscilloscope or logic analyzer connected to the output PMOD pins to inspect the exact generated waveforms and verify the safety clamp thresholds.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | enable | pwm_out | duty_in[0] |
| 1 | period_in[0] | comp_pwm_out | duty_in[1] |
| 2 | period_in[1] | unused_out_2 | duty_in[2] |
| 3 | period_in[2] | unused_out_3 | duty_in[3] |
| 4 | period_in[3] | unused_out_4 | unused_io_4 |
| 5 | invert | unused_out_5 | unused_io_5 |
| 6 | unused_in_6 | unused_out_6 | unused_io_6 |
| 7 | unused_in_7 | unused_out_7 | unused_io_7 |