545 Quadrature sine generator
545 : Quadrature sine generator
- Author: Framcesco Osti
- Description: A Quadrature Sine Direct Digital Synthetizer with PCM outputs
- GitHub repository
- Open in 3D viewer
- Clock: 50000000 Hz
How it works
This project generates two sinusoidal waveforms with a fixed 90° phase offset (I/Q signals) using Direct Digital Synthesis (DDS) techniques. The output is presented on output in Pulse Code Modulation via two first order Sigma-Delta modulators. DSS block can be prescaled by sending the prescaler value through SPI port.
Oscillator design is based on the following paper: J. Nam, A Study of Sinusoid Generation Using Recursive Algorithms
Block diagram
PINPUT
Inputs:
spi_clk = uo_in[0]spi_cs = uo_in[1]spi_miso = uo_in[2]
Outputs:
pcm_sin = uo_out[0]pcm_sin_n = uo_out[1]pcm_cos = uo_out[2]pcm_cos_n = uo_out[3]
How to test
Basic test
- Reset device by putting
rst_n = 0while providing a clock signal cycle onclkpin. - While keeping
spi_cs = 0provide 50MHz clock toclkpin, a 1kHz PCM sine and cosine signal should be visible respectively onpcm_sinandpcm_cospins. pcm_sin_nandpcm_cos_npins are the negated counterparts.
Full test
- Buffer the outputs
pcm_sin,pcm_cos,pcm_sin_nandpcm_cos_nwith for example a 74AC244 Digital buffer IC and filter them with a RC filter (suggested cutoff frequecy 50-100 kHz range). - Observe sine and cosine analog outputs.
- Using SPI port, the prescaler
pre[15:0]cane be loaded with new value allowing for output signals frequency control. After reset prescaler default value is0x0124corresponding to 1kHz. In general output frequency is given by rougthlyf_sig = f_clk / pre[15:0] / 400
SPI timing diagram
Output wiring diagram
External hardware
Recomanded hardware:
- Digital buffer IC (e.g: 74AC244)
- n.2 RC filters
- R = 220 ohm
- C = 10 nF
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | SCK | PCM_SIN | |
| 1 | CS | PCM_COS | |
| 2 | MOSI | ||
| 3 | |||
| 4 | |||
| 5 | |||
| 6 | |||
| 7 |