129 CWRU CHIPS Simple Counter with 7-segment Display

// this array would be your instruction memory
unsigned char instructions[256] ={0x00000013, 0x00000013, 0x00000013, ...};
// to access the array, you need to do some indexing
// normal cpu operation

// we have a register named curr_instr
unsigned char curr_instr;

// we use a for loop here, the counter variable
// i is just like our program counter
for (int i = 0; i < 256; i++) {
    curr_instr = instructions[i];
}

    wire [WIDTH-1:0] mem [0:DEPTH-1];

initial begin
    $readmemh("program.hex", mem);
end

add x3, x1, x2

addi x3, x1, 1

// Example: sign-extending a 12-bit I-type immediate
assign imm_out = {{20{instr[31]}}, instr[31:20]};

module alu (
    input  [31:0] op1,
    input  [31:0] op2,
    input  [3:0]  alu_ctrl,
    output reg [31:0] res,
    output zero_flag
);
    always @(*) begin
        case (alu_ctrl)
            4'b0000: res = op1 & op2;          // AND
            4'b0001: res = op1 | op2;          // OR
            4'b0010: res = op1 + op2;          // ADD
            4'b0110: res = op1 - op2;          // SUB
            4'b0111: res = (op1 < op2) ? 1 : 0; // SLT
            4'b1101: res = op1 ^ op2;          // XOR
            4'b1110: res = op1 << op2[4:0];    // SLL
            4'b1111: res = op1 >> op2[4:0];    // SRL
            default: res = 32'b0;
        endcase
    end
    assign zero_flag = (res == 32'b0);
endmodule

module data_memory (
    input         clk,
    input  [31:0] addr,
    input  [31:0] wr_data,
    input         MemRead,
    input         MemWrite,
    output [31:0] rd_data
);
    reg [31:0] mem [0:255];  // 256 words of data memory

    always @(posedge clk) begin
        if (MemWrite)
            mem[addr[9:2]] <= wr_data;  // word-aligned write
    end

    assign rd_data = MemRead ? mem[addr[9:2]] : 32'b0;
endmodule

PC → Instruction Memory → [opcode/rs1/rs2/rd/funct3/funct7]
                              ↓              ↓
                        Control Unit    Register File (read rs1, rs2)
                              ↓              ↓
                         ALUSrc mux ← rs2 or Immediate Generator
                              ↓
                             ALU → res → MemToReg mux → Register File (write rd)
                                          ↑
                                     Data Memory (if Load)

# Fibonacci sequence in RISC-V assembly
# x1 = F(n-2), x2 = F(n-1), x3 = F(n), x10 = loop counter

    addi x1, x0, 0       # F(0) = 0
    addi x2, x0, 1       # F(1) = 1
    addi x10, x0, 10     # compute 10 terms

loop:
    add  x3, x1, x2      # F(n) = F(n-1) + F(n-2)
    add  x1, x0, x2      # x1 = old x2
    add  x2, x0, x3      # x2 = new F(n)
    sw   x3, 0(x0)       # store result to data memory (addr 0)
    addi x10, x10, -1    # decrement counter
    bne  x10, x0, loop   # if counter != 0, loop