484 8-bit LFSR Circuit
484 : 8-bit LFSR Circuit
- Author: Satya Roop Bankuru
- Description: Sequential PRNG block using Verilog.
- GitHub repository
- Open in 3D viewer
- Clock: 50000000 Hz
8-Bit LFSR Pseudo-Random Circuit
Designed for digital VLSI training module parameters.
Core Topology
This design generates pseudo-random sequences using an active feedback polynomial shift mechanism: $x^8 + x^6 + x^5 + x^4 + 1$
Validation Guide
- Hold
rst_nlow to inject the0x01processing seed. - Assert
rst_nhigh to begin random cycling. - Observe the generated unique sequences change across the 8-bit
uo_outpins on each clock cycle edge.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | unused | out0 | unused |
| 1 | unused | out1 | unused |
| 2 | unused | out2 | unused |
| 3 | unused | out3 | unused |
| 4 | unused | out4 | unused |
| 5 | unused | out5 | unused |
| 6 | unused | out6 | unused |
| 7 | unused | out7 | unused |