384 teenytpu
384 : teenytpu
- Author: joannec34
- Description: 2x2 INT8 systolic-array TPU with SPI memory interface
- GitHub repository
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- Clock: 50000000 Hz
How it works
TeenyTPU is a 2x2 INT8 systolic array TPU designed. At its core, it features a 2x2 grid of Processing Elements (PEs) that can perform matrix multiplication operations on INT8 data, resulting in 16-bit partial sum sequences.
SPI Pin Mapping
ui[0]: SPI SCLKui[1]: SPI CS_Nui[2]: SPI MOSIuo[0]: SPI MISOuo[1]: BUSY flaguo[2]: DONE flag
Architecture Overview
- SPI Slave Bridge — deserialises SPI transactions from an external host into register writes and command pulses. Uses 2-FF CDC synchronisers for SCLK, CS_N, and MOSI. Supports five opcodes:
0x01 WRITE_WEIGHT— load an 8-bit weight into a selected column/row.0x02 LOAD_INPUT— load an 8-bit activation into a selected row.0x03 CMD_START— trigger the compute FSM.0x04 READ_RESULT— read back two 16-bit partial sums from a selected column.0x05 READ_STATUS— read the{done, busy}status byte.
- Control FSM — sequences weight loading, shadow→active switch, activation feeding, draining, and result readback through six states (
IDLE → LOAD_W → SWITCH → FEED → DRAIN → DONE). - 2×2 Systolic Array — four PE instances connected in a grid. Activations flow left -> right, partial sums flow top -> bottom, and weights propagate top→bottom during loading.
How to test
To test the TeenyTPU, you must implement an SPI master to drive the designated ui pins.
- Hardware Reset: Provide a clock signal (
clk) and assertrst_nlow briefly to reset the FSM and the systolic array. - Load Weights: Assert
CS_Nlow, send the0x01opcode, followed by the column index (e.g.,0x00), and then the two 8-bit weights for that column. DeassertCS_N. Repeat this for column 1. - Load Activations: Assert
CS_Nlow, send the0x02opcode, followed by the row index (e.g.,0x00), and the 8-bit activation value. DeassertCS_N. Repeat this for row 1. - Trigger Computation: Send the
0x03opcode to initiate computation. Thebusypin (uo[1]) will assert high. - Poll Status: Wait for the
donepin (uo[2]) to assert high, which indicates that the systolic array has finished computation. Alternatively, you can use the0x05opcode to read the{6'b0, done, busy}status byte repeatedly. - Read Results: Send the
0x04opcode followed by the column index (0x00or0x01). The TPU will respond by shifting out 16 bits of result data (MISO) representing the partial sums of that column.
External hardware
An SPI master connected to ui[0] (SCLK), ui[1] (CS_N), ui[2] (MOSI), and uo[0] (MISO).
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | spi_sclk | spi_miso | |
| 1 | spi_cs_n | busy | |
| 2 | spi_mosi | done | |
| 3 | |||
| 4 | |||
| 5 | |||
| 6 | |||
| 7 |