484 BIST-8: Built-In Self-Test for 8-bit CLA Adder
484 : BIST-8: Built-In Self-Test for 8-bit CLA Adder
- Author: Mario Garcia Jimenez
- Description: BIST architecture for an 8-bit Carry-Lookahead Adder. Includes 12-bit LFSR pattern generator, 16-bit MISR response compactor, fault injection and 4-state FSM controller. Golden signature 0xCF77.
- GitHub repository
- Open in 3D viewer
- Clock: 10000000 Hz
How it works
BIST-8 implements a complete Built-In Self-Test architecture for an 8-bit Carry-Lookahead Adder (CLA).
The design has two modes of operation:
Normal mode (bist_en=0): The CLA adder operates as a standard 8-bit adder. Operand A is provided via ui_in[7:2] and uio_in[7:6], operand B via uio_in[5:0]. The result appears on uo_out[7:3].
BIST mode (bist_en=1): The circuit self-tests in 4095 clock cycles automatically:
- A 12-bit LFSR (polynomial x^12+x^11+x^10+x^4+1, seed 0xACE) generates 4095 unique test vector pairs.
- Each pair is applied to the CLA adder (Circuit Under Test).
- Each response is compacted into a 16-bit MISR (polynomial x^16+x^15+x^2+1).
- After 4095 cycles, the MISR signature is compared against the golden reference 0xCF77.
- If they match, bist_pass=1. Otherwise bist_fail=1.
A fault injection input (fault_inject) forces bit 3 of the adder output to stuck-at-0, allowing demonstration of fault detection. The faulty signature is 0x927F, which differs from the golden value, proving the BIST detects the fault.
The FSM has 4 states: IDLE -> BIST_RUN -> COMPARE -> DONE.
How to test
Normal mode:
- Set ui_in[0]=0 (bist_en=0)
- Apply operand A on ui_in[7:2] and uio_in[7:6]
- Apply operand B on uio_in[5:0]
- Read result on uo_out[7:3]
BIST mode (no fault):
- Assert reset (rst_n=0 then rst_n=1)
- Set ui_in[0]=1, ui_in[1]=0
- Wait 4095 clock cycles for uo_out[2]=1 (bist_done)
- Expected: uo_out[0]=1 (bist_pass), uo_out[1]=0 (bist_fail)
BIST mode with fault injection:
- Assert reset
- Set ui_in[0]=1, ui_in[1]=1
- Wait for uo_out[2]=1 (bist_done)
- Expected: uo_out[1]=1 (bist_fail) - fault detected
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | bist_en | bist_pass | cycle_count[0] |
| 1 | fault_inject | bist_fail | cycle_count[1] |
| 2 | a_in[0] | bist_done | cycle_count[2] |
| 3 | a_in[1] | sum_out[3] | cycle_count[3] |
| 4 | a_in[2] | sum_out[4] | cycle_count[4] |
| 5 | a_in[3] | sum_out[5] | cycle_count[5] |
| 6 | a_in[4] | sum_out[6] | a_in[6] |
| 7 | a_in[5] | sum_out[7] | a_in[7] |