358 Stochastic neuron + STDP controller (merged, GF180)
358 : Stochastic neuron + STDP controller (merged, GF180)
- Author: Prof. Santhosh Sivasubramani, IIT Delhi
- Description: GF180mcuD merged-pair cell: an 8-bit saturating LIF/stochastic neuron with an 8-entry sigmoid LUT, 8-bit Galois LFSR, programmable refractory, per-clock leak, host-triggered stimulus on ext_input rising edge, homeostatic theta adaptation over a 256-clock window (theta_live floats between theta_min and theta_max depending on spike count vs reg_target), and a 16-clock Bayesian confidence window emitting a 2-bit conf output. The second block is an STDP controller with 8-bit pre/post spike traces, per-clock exponential-shift decay (reg_tau_plus / reg_tau_minus), an anti-Hebbian polarity bit and optional reward-gated learning; on every LTP event (post spike with pre trace != 0) or LTD event (pre spike with post trace != 0) a 1-cycle weight_update pulse is emitted along with a learn_dir bit and a magnitude latch read over SPI. All registers are programmable via an 8-bit-data SPI mode-0 slave shared with the other TTGF26a tiles. 25 MHz signoff.
- GitHub repository
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- Clock: 25000000 Hz
tt_um_santhosh_stoch_stdp_pair_gf
TTGF26a Scenario B tile 1 — merged stochastic/LIF neuron + STDP learning controller on GF180mcuD.
How it works
The tile combines an 8-bit saturating leaky-integrate-and-fire (LIF) neuron
with a stochastic mode (fire when lfsr < sig_lut[v_mem[7:5]]), homeostatic
theta adaptation over a 256-clock window, and a 16-clock Bayesian confidence
counter. A second block is an STDP controller with 8-bit pre/post traces,
per-clock exponential-shift decay, an anti-Hebbian polarity bit, and optional
reward-gated learning. On every LTP or LTD event the controller emits a
1-cycle weight_update pulse together with learn_dir and latches the
magnitude in R_LAST_MAG for host readback.
All registers are programmable via a shared 8-bit SPI mode-0 slave (same module used by the other TTGF26a tiles).
How to test
- Program the neuron (
R_STIM,R_THETA,R_LEAK,R_SIG_LUT[0..7],R_POLY,R_TARGET,R_THETA_MIN,R_THETA_MAX) and the STDP controller (R_TAU_PLUS,R_TAU_MINUS,R_LTP_LUT[0..7],R_LTD_LUT[0..3],R_STDP_CTRL) via SPI. - Drive
ui_in[0]to pick LIF or stochastic mode. - Assert
ui_in[4](or set CTRL[3]) to enable homeostatic adaptation. - Assert
ui_in[5](or set CTRL[4]) to enable Bayesian confidence counting. - Drive
ui_in[2]high and writeR_STDP_CTRL[0]=1to enable learning. - Pulse
ui_in[1](ext_input) once per presynaptic spike; observeuo_out[0]= post-synaptic spike anduo_out[1]= 1-cycle weight-update pulse. - Read
R_VMEM,R_TRACE_PRE,R_TRACE_POST,R_LAST_MAG,R_BAYES_CONF,R_THETA_LIVE,R_STATUSvia SPI to observe state.
External hardware
Only a microcontroller (or FPGA) driving the SPI slave is required. Any
spike-train source can be wired to ui_in[1].
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | mode_sel (0=LIF, 1=stochastic) | spike_out (post-synaptic spike) | spi_cs_n (input) |
| 1 | ext_input (pre-synaptic spike / drive) | weight_update (1-cycle STDP pulse) | spi_mosi (input) |
| 2 | learn_en | theta_hi (theta_live at ceiling) | spi_miso (output) |
| 3 | reward (R-STDP gate) | theta_lo (theta_live at floor) | spi_sck (input) |
| 4 | homeostatic_en | bayes_conf[0] | reserved (input, tied off) |
| 5 | bayes_en | bayes_conf[1] | reserved (input, tied off) |
| 6 | reserved | learn_dir (1=LTP, 0=LTD) | reserved (input, tied off) |
| 7 | reserved | busy (refractory OR weight_update in flight) | reserved (input, tied off) |