
Design was synthesized to gate level using Dyno-SV by hand, using the command below
dyno-sv --liberty=sky130_fd_sc_hd.lib project_rtl.v -o=src/project.v
Check if correct values are being output.
None!
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | input word bit 0 | idx of first set bit, bit 0 | idx of third set bit, bit 0 |
| 1 | input word bit 1 | idx of first set bit, bit 1 | idx of third set bit, bit 1 |
| 2 | input word bit 2 | idx of first set bit, bit 2 | idx of third set bit, bit 2 |
| 3 | input word bit 3 | idx of first set bit, valid | idx of third set bit, valid |
| 4 | input word bit 4 | idx of second set bit, bit 0 | counter bit 0 |
| 5 | input word bit 5 | idx of second set bit, bit 1 | counter bit 1 |
| 6 | input word bit 6 | idx of second set bit, bit 2 | input registered (1) or comb (0) |
| 7 | input word bit 7 | idx of second set bit, valid | output registered (1) or comb (0) |