200 spi_slave_ctrl
200 : spi_slave_ctrl
- Author: felixzhou
- Description: spi slave for register r&w
- GitHub repository
- Open in 3D viewer
- Clock: 50000000 Hz
How it works
This Module simulate a simple spi slave controller for internal registers read&write. sys_clk should 4x faster than spi_clk at least.
How to test
// -------------------------- spi read reg timing -------------------------------- // // mosi [cmd] [addrN] X X X X // miso X X X datN datN+1 datN+2
// -------------------------- spi write reg timing ------------------------------ // // mosi [cmd] [addrN] datN datN+1 datN+2 ...
External hardware
a external controller connect spi_ncs/spi_clk/spi_mosi/spi_miso
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | SPI_NCS | SPI_MISO | |
| 1 | SPI_CLK | FIFO_OUT_SERIAL | |
| 2 | SPI_MOSI | ||
| 3 | |||
| 4 | |||
| 5 | |||
| 6 | |||
| 7 |