133 transformer-attention-engine
133 : transformer-attention-engine
- Author: Tarik Ibrahimovic
- Description: Transformer attention engine with a credit based pipeline
- GitHub repository
- Open in 3D viewer
- Clock: 60000000 Hz
Here you go—drop-in text for your datasheet. It’s short, objective, and matches the I/O in your module.
How it works
-
Purpose. Computes one dot-product over 4 terms from sequential 8-bit Q0.7 samples, then outputs
exp(mac/2)in UQ3.6 (9-bit) format. -
Interface.
-
Inputs:
ui_in[7:0]— data (Q0.7 signed).uio_in[0]—vld_slv_in(input valid).uio_in[3]—rdy_mst_in(output handshake from master).
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Outputs:
uo_out[7:0]— result LSBs (UQ3.6).uio_out[4]— result MSB (bit 8).uio_out[2]—vld_mst_out(output valid).uio_out[1]—rdy_slv_out(always1, input always ready).
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Operation.
- The core ingests pairs of consecutive samples. On the first valid, it latches the value; on the second valid, it multiplies the new sample by the latched one and accumulates into a 17-bit MAC.
- After 4 such products (i.e., 8 input samples total, provided as 4 back-to-back pairs), it computes
exp(mac/2)via theexblock and exposes the 9-bit UQ3.6 result. vld_mst_outgoes high to signal a ready result; it de-asserts once the master assertsrdy_mst_in.
How to test
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Reset & enable. Drive clock, hold
rst_n=0for ≥1 cycle, then setrst_n=1. Keepena=1. -
Feed inputs (4 pairs = 8 samples). For each of 4 pairs:
- First of pair: place sample A on
ui_in, setuio_in[0]=1for one (or more) cycle(s). - Second of pair: place sample B on
ui_in, setuio_in[0]=1again → the productA*Bis accumulated. - You may keep
uio_in[0]=0when idle. Input is always ready (uio_out[1]=1).
- First of pair: place sample A on
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Read result.
- After the 4th pair,
uio_out[2]=1(output valid). - Read 9-bit UQ3.6 result:
{uio_out[4], uo_out[7:0]}. - Acknowledge by setting
uio_in[3]=1for ≥1 cycle;uio_out[2]will drop.
- After the 4th pair,
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Repeat. Provide the next 4 pairs to get the next result.
Notes.
- Input format: Q0.7 (signed).
- Output format: UQ3.6 (unsigned 9-bit).
- Input back-pressure is not asserted (module is always ready).
External hardware
i will
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | ui_in[0] | uo_out[0] | uio_out[0] |
| 1 | ui_in[1] | uo_out[1] | uio_out[1] |
| 2 | ui_in[2] | uo_out[2] | uio_out[2] |
| 3 | ui_in[3] | uo_out[3] | uio_out[3] |
| 4 | ui_in[4] | uo_out[4] | uio_out[0] |
| 5 | ui_in[5] | uo_out[5] | uio_out[1] |
| 6 | ui_in[6] | uo_out[6] | uio_out[2] |
| 7 | ui_in[7] | uo_out[7] | uio_out[3] |