194 Zilog Z80 :: Quicker, easier and cheaper to make your own chip!

How it works

On April 15 of 2024 Zilog has announced End-of-Life for Z80, one of the most famous 8-bit CPUs of all time. It is a time for open-source and hardware preservation community to step in with a Free and Open Source Silicon (FOSS) replacement for Zilog Z80.

The implementation is based around Guy Hutchison's TV80 Verilog core.

The future work

Add thorough instruction (including 'illegal') execution tests ZEXALL to testbench
Compare different implementations: Verilog core A-Z80, Netlist based Z80Explorer
Create gate-level layouts that would resemble the original Z80 layout. Zilog designed Z80 by manually placing each transistor by hand.
Tapeout QFN44 package
Tapeout DIP40 package

Z80 technical capabilities

nMOS original frequency 4MHz. CMOS frequency up to 20 MHz. This tapeout on 130 nm is expected to support frequency up to 50 MHz.
158 instructions including support for Intel 8080A instruction set as a subset.
Two sets of 6 general-purpose reigsters which may be used as either 8-bit or 16-bit register pairs.
One maskable and one non-maskable interrupt.
Instruction set derived from Datapoint 2200, Intel 8008 and Intel 8080A.

Z80 registers

AF: 8-bit accumulator (A) and flag bits (F)
BC: 16-bit data/address register or two 8-bit registers
DE: 16-bit data/address register or two 8-bit registers
HL: 16-bit accumulator/address register or two 8-bit registers
SP: stack pointer, 16 bits
PC: program counter, 16 bits
IX: 16-bit index or base register for 8-bit immediate offsets
IY: 16-bit index or base register for 8-bit immediate offsets
I: interrupt vector base register, 8 bits
R: DRAM refresh counter, 8 bits (msb does not count)
AF': alternate (or shadow) accumulator and flags (toggled in and out with EX AF, AF' )
BC', DE' and HL': alternate (or shadow) registers (toggled in and out with EXX)

Z80 Pinout

                    ,---------.__.---------.
         <--    A11 |1                   40| A10    -->       
         <--    A12 |2                   39| A9     -->        
         <--    A13 |3       Z80 CPU     38| A8     -->        
         <--    A14 |4                   37| A7     -->        
         <--    A15 |5                   36| A6     -->
         -->    CLK |6                   35| A5     -->
         <->     D4 |7                   34| A4     -->
         <->     D3 |8                   33| A3     -->            
         <->     D5 |9                   32| A2     -->            
         <->     D6 |10                  31| A1     -->            
                VCC |11                  30| A0     -->           
         <->     D2 |12                  29| GND           
         <->     D7 |13                  28| /RFSH  -->          
         <->     D0 |14                  27| /M1    -->           
         <->     D1 |15                  26| /RESET <--      
         -->   /INT |16                  25| /BUSRQ <--      
         -->   /NMI |17                  24| /WAIT  <--      
         <--  /HALT |18                  23| /BUSAK -->     
         <--  /MREQ |19                  22| /WR    -->       
         <--  /IORQ |20                  21| /RD    -->       
                    `----------------------'

How to test

Hold all bidirectional pins (Data bus) low to make CPU execute NOP instruction. NOP instruction opcode is 0. Hold all input pins high to disable interrupts and signal that data bus is ready.

Every 4th cycle 8-bit value on output pins (Address bus low 8-bit) should monotonously increase.

     Timing diagram, input pins

      Z80CLK____      ____      ____      ____      ____      ____         
         __/    \____/    \____/    \____/    \____/    \____/    `____ ...
           |        |         |         |         |         |
           |        |         |         |         |         |

      /RESET___________________________________________________________
         __/
      /WAIT ___________________________________________________________
         __/
      /INT  ___________________________________________________________
         __/
      /NMI  ___________________________________________________________
         __/
      /BUSRQ___________________________________________________________
         __/

      D7..D0             NOP       NOP       NOP       NOP       NOP
         __ XXXXXXXXX ___#00___ ___#00___ ___#00___ ___#00___ ___#00___

      Expected signals on output pins
      /M1   _________                    ____________________
                     \__________________/                    \_________
      /MREQ ___________________          ______________________________
                               \________/ 
      /RD   ___________________          ______________________________
                               \________/
      A0..A7         
         __ XXXXXXXXX ___#00___ ___#00___ XXXXXXXXX XXXXXXXXX ___#01___

External hardware

Bus de-multiplexor, external memory, 8-bit computer such as ZX Spectrum.

Alternatively the RP2040 on the TinyTapeout test PCB can be used to simulate RAM and I/O.

#	Input	Output	Bidirectional
0	/WAIT	/M1, A0, A8	D0
1	/INT	/MREQ, A1, A9	D1
2	/NMI	/IORQ, A2, A10	D2
3	/BUSRQ	/RD, A3, A11	D3
4	CONFIG -- 00: short MREQ IORQ RD; 01: short MREQ IORQ RD starting early	/WR, A4, A12	D4
5	CONFIG -- 10: long MREQ IORQ; 11: long MREQ IORQ RD starting early	/RFSH, A5, A13	D5
6	MUX -- address lo/hi bits on the output pins	/HALT, A6, A14	D6
7	MUX -- control signals on the output pins	/BUSAK, A7, A15	D7

194 Zilog Z80

194 : Zilog Z80

How it works

How to test

External hardware

IO

Chip location