134 sky130_as_sc_hs test
134 : sky130_as_sc_hs test
- Author: Tholin
- Description: Testing sky130_as_sc_hs SCL
- GitHub repository
- Open in 3D viewer
- Clock: 10000000 Hz
How it works
A simple 6-bit MCU, but built with the sky130_as_sc_hs SCL. Check here for documentation on the CPU architecture.
How to test
Wire up a 25Q32 (or compatible) spiflash with valid bytecode using the SDO, SDI, SCLK and CSb pins, pull INT low and HS low. A test program is included in this repo under test/asm/ which counts up on the PA lines.
External hardware
25Q32 (or compatible) spiflash to hold CPU bytecode. Anything you want on the GPIO lines.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | PB[0] | PC[0] | PA[0] |
| 1 | PB[1] | PC[1] | PA[1] |
| 2 | PB[2] | PC[2] | PA[2] |
| 3 | PB[3] | PC[3] | PA[3] |
| 4 | PB[4] | PC[4] | PA[4] |
| 5 | PB[5] | PC[5] | PA[5] |
| 6 | INT | SDO | HS |
| 7 | SDI | SCLK | CSb |