The project generates a Pulse Width Modulated (PWM) waveform with a user-defined duty cycle. An internal counter continuously increments with each clock cycle. The duty cycle value, provided as input, is compared against this counter. Whenever the counter value is less than the duty cycle value, the output stays HIGH; otherwise, it goes LOW. This produces a PWM signal where the ON time (duty cycle) can be adjusted.
Provide a clock signal to the design. Set the duty cycle input value (e.g., 25%, 50%, 75%) via input pins. Observe the PWM output waveform on an oscilloscope or logic analyzer. A low duty cycle will give shorter ON pulses. A high duty cycle will give longer ON pulses. Verify that the output waveform changes according to the duty cycle input.
Oscilloscope or Logic Analyzer (to observe the PWM waveform)
# | Input | Output | Bidirectional |
---|---|---|---|
0 | Duty cycle bit 0 | PWM output | Unused |
1 | Duty cycle bit 1 | PWM output copy | Unused |
2 | Duty cycle bit 2 | Unused | Unused |
3 | Duty cycle bit 3 | Unused | Unused |
4 | Duty cycle bit 4 | Unused | Unused |
5 | Duty cycle bit 5 | Unused | Unused |
6 | Duty cycle bit 6 | Unused | Unused |
7 | Unused | Unused | Unused |