288 PLC-PRG
288 : PLC-PRG
- Author: Shruthi Rekhana
- Description: Implements a simple PLC-style programmable logic controller in Verilog.
- GitHub repository
- Open in 3D viewer
- Clock: 1000000 Hz
How it works
This project implements a PLC-PRG (Programmable Logic Controller – Program) in Verilog.
It mimics the behavior of a simple PLC by reading digital inputs (ui[7:0]), processing the logic, and driving outputs (uo[7:0]) based on programmed control rules.
The design is combinational/sequential depending on the configuration. Inputs can represent push buttons or sensors (e.g., START, STOP, RESET), and outputs can represent actuators such as LEDs, relays, or motors.
The Verilog code models the basic scan cycle of a PLC:
- Read Inputs (ui pins)
- Execute Logic (ladder/boolean operations implemented in Verilog)
- Update Outputs (uo pins)
This makes it possible to prototype small automation tasks directly on silicon.
How to test
-
Connect input pins (
ui[0]–ui[7]) to switches, buttons, or FPGA I/O signals.- Example:
ui[0]: STARTui[1]: STOPui[2]: RESET- Others: user-defined
- Example:
-
Observe output pins (
uo[0]–uo[7]).- Example:
uo[0]: Motor control (ON/OFF)uo[1]: Status LED- Others: user-defined
- Example:
-
Simulation:
- Run the provided testbench to verify that the outputs follow PLC-style logic rules.
- Example: START sets motor ON until STOP is pressed.
-
On silicon:
- Wire push buttons to inputs.
- Observe LEDs or actuators connected to outputs.
External hardware
- Optional push buttons / switches → to drive input pins.
- LEDs or relays → to observe output states.
- No mandatory external hardware is required; the design works with raw digital inputs and outputs.
Example use case
ui[0](START) turns ONuo[0](Motor LED).ui[1](STOP) turns OFFuo[0].ui[2](RESET) clears all outputs.
This demonstrates how a simple PLC program can be realized directly in Verilog and fabricated with Tiny Tapeout.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | IN0 | OUT0 | |
| 1 | IN1 | OUT1 | |
| 2 | IN2 | OUT2 | |
| 3 | IN3 | OUT3 | |
| 4 | IN4 | OUT4 | |
| 5 | IN5 | OUT5 | |
| 6 | IN6 | OUT6 | |
| 7 | IN7 | OUT7 |