998 Axi4_Lite
998 : Axi4_Lite
- Author: Team_13
- Description: Communication Protocol
- GitHub repository
- Open in 3D viewer
- Clock: 50000000 Hz
AXI4-Lite Top Project
Overview
This project implements a self-contained AXI4-Lite system with a master and a slave connected inside a top-level wrapper (axi4lite_top).
It exposes a simple control interface so that reads and writes can be performed without directly driving AXI signals.
How It Works
- The top module (
axi4lite_top) instantiates:- An AXI4-Lite Master
- An AXI4-Lite Slave
- Instead of requiring the user to control all AXI signals, the top module provides a simplified interface:
ui_in[0]→ Start Writeui_in[2:1]→ Write Addressuio_in→ Write Dataui_in[4]→ Start Readui_in[3:2]→ Read Address
- When a transaction is started:
- The master drives the appropriate AXI4-Lite signals.
- The slave responds according to AXI protocol.
- When the transaction finishes,
uo_out[0]goes high (Done). - On reads, the data is returned via
uio_out.
Effectively, this module hides AXI4-Lite complexity and lets the user test simple memory-mapped transactions.
How to Test
Two types of testbenches are provided:
1. Verilog Testbench
- Located at
sim/axi4lite_tb.v. - Runs a reset → write → read → check sequence.
- Displays results in the simulator console.
2. Cocotb Testbench
- Located at
sim/test_axi4lite.py. - Uses Python for more flexible verification.
- Run with Icarus Verilog:
make SIM=icarus TOPLEVEL=axi4lite_top MODULE=test_axi4lite
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | start_write | data_read[0] | data_write[0] |
| 1 | write_addr[0] | data_read[1] | data_write[1] |
| 2 | write_addr[1] | data_read[2] | data_write[2] |
| 3 | start_read | data_read[3] | data_write[3] |
| 4 | read_addr[0] | data_read[4] | data_write[4] |
| 5 | read_addr[1] | data_read[5] | data_write[5] |
| 6 | data_read[6] | data_write[6] | |
| 7 | data_read[7] | data_write[7] |