196 TTSKY25A Register File Test
196 : TTSKY25A Register File Test
- Author: Sylvain Munaut
- Description: Test structures for a future register file macro
- GitHub repository
- Open in 3D viewer
- Clock: 0 Hz
How it works
It's basically a SRAM with 1 write port and 2 read ports. See design data for information
How to test
No test procedure has been written yet and it's not meant to be tested by the "demo board" but instead on a dedicated test platform.
External hardware
To do any meaningful timing testing you'll need some FPGA hardware to drive the various control signal in sequence with precise timings.
The exact testing platform is still TBD.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | tbd | tbd | tbd |
| 1 | tbd | tbd | tbd |
| 2 | tbd | tbd | tbd |
| 3 | tbd | tbd | tbd |
| 4 | tbd | tbd | tbd |
| 5 | tbd | tbd | tbd |
| 6 | tbd | tbd | tbd |
| 7 | tbd | tbd | tbd |