557 MiniRISC-FSM
557 : MiniRISC-FSM
- Author: AGhani - Emirates Chips Competence - Design1
- Description: Minimal RISC-style FSM core with LOAD, ADD, SUB, and STORE instructions
- GitHub repository
- Open in 3D viewer
- Clock: 50000000 Hz
How it works
This project implements a simple MiniRISC processor using an FSM-based control unit.
- The design fetches an instruction (provided via the
ui_inpins). - The FSM steps through the instruction cycle: fetch → decode → execute → write-back.
- An accumulator register (ACC) stores intermediate results.
- The output pins (
uo_out) reflect the current ACC value or operation result. - Internal state is tracked via a finite state machine, ensuring each instruction executes deterministically across multiple clock cycles.
The goal is to demonstrate how a minimal RISC-like processor can be built with simple Verilog, synthesized for Tiny Tapeout, and verified through simulation and hardware testing.
How to test
-
Simulation (before fabrication):
- Use the provided
tb.vtestbench with Icarus Verilog and cocotb.
- Use the provided
-
On real hardware
- The packaged chip will be mounted on a Tiny Tapeout test PCB with a Raspberry Pi as the host.
- Reset the chip using the provided reset control.
- Send instructions sequentially via
ui_inpins from the Raspberry Pi GPIO. - Observe
uo_outto capture results of operations. - Compare against the expected outputs (the same instruction sequence used in simulation).
This allows direct validation of the FSM processor on silicon, mirroring the cocotb verification flow.
External hardware
None
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | ui_in[0] | uo_out[0] | uio_out[0] |
| 1 | ui_in[1] | uo_out[1] | uio_out[1] |
| 2 | ui_in[2] | uo_out[2] | uio_out[2] |
| 3 | ui_in[3] | uo_out[3] | uio_out[3] |
| 4 | ui_in[4] | uo_out[4] | uio_out[4] |
| 5 | ui_in[5] | uo_out[5] | uio_out[5] |
| 6 | ui_in[6] | uo_out[6] | uio_out[6] |
| 7 | ui_in[7] | uo_out[7] | uio_out[7] |