169 Duty Cycle Meter
169 : Duty Cycle Meter
- Author: Alida Bruka
- Description: This system checks for an input PWM signal and outputs its duty cycle from 0 to 127
- GitHub repository
- Open in 3D viewer
- Clock: 50000000 Hz
How it works
There is FSM that counts how many times the input signal is "ON" in a fixed time window, than it calculates the duty cycle
How to test
just put a PWM signal to the input ui.in[0] and check the first 7 bits of uo.out (the duty cycle value) and the bit uo.out[7] (the valid signal). The value 127 corresponds to a duty cycle of 100%
External hardware
A signal generator or PWM generator for the input and a logic state analyzer to check the output
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | sign in | duty_cycle[0] | |
| 1 | duty_cycle[1] | ||
| 2 | duty_cycle[2] | ||
| 3 | duty_cycle[3] | ||
| 4 | duty_cycle[4] | ||
| 5 | duty_cycle[5] | ||
| 6 | duty_cycle[6] | ||
| 7 | valid |