
This project implements an 8-bit signed baugh-wooley multiplier. The two input operands are provided through:
ui_in -> first operand (A), uio_in -> second operand (B)
The Baugh-Wooley Architecture The multiplier generates partial products using bitwise AND operations between the bits of A and B. These partial products are arranged in a grid and shifted according to their bit positions. The shifted partial products are then summed using a tree reduction structure to produce the final 16-bit result A correction bit pattern is then applied to correct for two-complement signed multiplicaiton.
The final product is split across the outputs:
uo_out → lower 8 bits of the result, uio_out → upper 8 bits of the result
To test the multiplier:
Apply two 8-bit signed values:
Put operand A on ui_in, Put operand B on uio_in
Wait for one clock cycle
Read the result:
Lower 8 bits from uo_out Upper 8 bits from uio_out
Combine them to get the full 16-bit signed result
Example:
Input: ui_in = 20, uio_in = 30 Output: {uio_out, uo_out} = 600
The design supports both positive and negative values using two’s complement representation.
None
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | Data bit 0 / Output select (cmd[0]) | Product byte bit 0 (low byte) | Product bit 8 (high byte) |
| 1 | Data bit 1 | Product byte bit 1 | Product bit 9 |
| 2 | Data bit 2 | Product byte bit 2 | Product bit 10 |
| 3 | Data bit 3 | Product byte bit 3 | Product bit 11 |
| 4 | Data bit 4 | Product byte bit 4 | Product bit 12 |
| 5 | Data bit 5 | Product byte bit 5 | Product bit 13 |
| 6 | opcode LSB (00=load A, 01=load B, 10=start) | Product byte bit 6 | Product bit 14 |
| 7 | opcode MSB | Product byte bit 7 | Product bit 15 |