718 Project Long Man: A Delay-Insensitive Interconnect
718 : Project Long Man: A Delay-Insensitive Interconnect
- Author: TCL Tyrants
- Description: A quasi-delay-insensitive die-to-die interconnect
- GitHub repository
- Open in 3D viewer
- Clock: 66000000 Hz
How it works
The core of this project is a quasi-asynchronous interconnect. Data is streamed in through an SPI interface, then the data is sent between from the TX to the RX, with an ACK signal between each transaction. After completion, data is streamed out of the SPI interface.
Instead of standard NULL convention where the TX and RX lines go low after each transaction, we instead read toggles on each line as a representation of new data. This essentially halves the switching rate of the TX-RX lanes with some minor added logic on the decoder and encoder.
As an example, observe the following transaction:
- T=time : TX-RX data : decoded value
- T=0 :
4'b0110:X - T=1 :
4'b1110:2'b11 - T=2 :
4'b1100:2'b01 - T=3 :
4'b1100:X
Here, the value 4'b0111 would be recieved on the RX side.
How to test
Connect the RX and TX sides together by tying UI[4:0] to UO[4:0].
Note that with two chips, you can instead tie the chips together.
The asyncronous interconnect is then controlled by the following steps: 0. Preform an active low reset
- Hold the CAPTURE line (
UIO[7]) high - Stream data over the SPI interface
2.1. MOSI (input) isUI[7]
2.2. SCLK isUIO[6]
2.3. MOSI gets read on posedge of SCLK - Pulse the LOAD line to start (
UI[5]) - TX and RX are now communicating
- When VLD (
UO[6]) goes high, drop the CAPTURE line - Stream RX data over the SPI interface
6.1. MISO (output) isUO[7]
6.2. MISO gets shifts on negedge of SCLK - After data is recieved, pulse the RDY line (
UI[6]) - Once DONE (
UO[5]) is asserted, restart from step 1
Note: steps 2 and 6 can be done at the same time, but step 1 must still be repeated on the next cycle.
It is also possible to instead pulse the CAPTURE line before reading the RX data.
External hardware
None.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | RX[0] | TX[0] | DBG_ADDR[0] |
| 1 | RX[1] | TX[1] | DBG_ADDR[1] |
| 2 | RX[2] | TX[2] | DBG_ADDR[2] |
| 3 | RX[3] | TX[3] | DBG_ADDR[3] |
| 4 | TX_ACK | RX_ACK | |
| 5 | LOAD | DONE | DBG_OUT |
| 6 | RDY | VLD | SCLK |
| 7 | MOSI | MISO | CAPTURE |