
A row of 4 DFFs are connected output to input (Q_n --> D_n+1). The last DFF is connected to the first via inverse Q.
Power on the IC. All outputs should be toggling at 1/4 of the input clock frequency.
A more in-depth test is to connect all four output to a logic analyzer. Verify that you see the following pattern when power is applied:
Q_1 1-1-1-1-0-0-0-0
Q_2 0-1-1-1-1-0-0-0
Q_3 0-0-1-1-1-1-0-0
Q_4 0-0-0-1-1-1-1-0
None
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | Q1 | ||
| 1 | Q2 | ||
| 2 | Q3 | ||
| 3 | Q4 | ||
| 4 | |||
| 5 | |||
| 6 | |||
| 7 |