
This project implements five different analog comparators based on standard logic cells. The analog inputs a[0] and a[1] are connected to the inputs V+ and V- of the comparators. Four comparators need an external clock signal, which is selected by the configuration tool.
Insert a constant signal to one of the analog input (V-) and a variable signal to the other analog input (V-). Observe the output. If V+ > V- is expected the output OutP_comp set to '1' and OutM_comp to '0'.
It's necessary a signal generator to generate the analog input values (an[0] and an[1]) and an osciloscope to visualize both the inputs and the outputs from the comparators.
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | VoutP_NAND | Vout_DIGOTA | |
| 1 | VoutM_NAND | ||
| 2 | VoutP_AO22 | ||
| 3 | VoutM_AO22 | ||
| 4 | VoutP_OAI211 | ||
| 5 | VoutM_OAI211 | ||
| 6 | VoutM_MX21 | ||
| 7 | VoutP_MX21 |
ua | PCB Pin | Internal index | Description |
|---|---|---|---|
| 0 | B4 | 10 | VinP |
| 1 | B5 | 11 | VinM |