
Uses a configuration of NAND gates to give OR logic.
IN0 and IN1 are inputs for NAND configured as an OR gate. OUT0 is output for NAND configured as an OR gate.
IN2 and IN3 are inputs for OR gate. OUT1 is output for OR gate.
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | IN0 | OUT0 | |
| 1 | IN1 | OUT1 | |
| 2 | IN2 | ||
| 3 | IN3 | ||
| 4 | |||
| 5 | |||
| 6 | |||
| 7 |