331 PD+PFD+FreqDiv

331 : PD+PFD+FreqDiv

Design render

How it works

Two inputs for phase and frequency comparison (PFD1IN and PFD2IN) using DFlip Flops and AND for reset, Two inputs for Phase comparison only (PD1IN and PD2IN), Clock Division for Feedback path in PLL configurations using Dflip flops

How to test

Flick the switches so that the waveforms lead or lag eachother or connect square wave signals as inputs.

External hardware

Could use input signal from sig gen or additional comparator with another signal.

IO

#InputOutputBidirectional
0PFD1INPFD1OUT
1PFD2INPFD2OUT
2DIVINTESTOUT1
3PD1TESTOUT2
4PD2DIV1
5UnusedDIV2
6UnusedDIV3
7PFDONPDOUT

Chip location

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